JAJSOW0A July   2022  – July 2023 TDP1204

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  4-Level Inputs
      2. 8.2.2  I/O Voltage Level Selection
      3. 8.2.3  HPD_OUT
      4. 8.2.4  Lane Control
      5. 8.2.5  Swap
      6. 8.2.6  Linear and Limited Redriver
      7. 8.2.7  Main Link Inputs
      8. 8.2.8  Receiver Equalizer
      9. 8.2.9  CTLE Bypass
      10. 8.2.10 Adaptive Equalization in HDMI 2.1 FRL
        1. 8.2.10.1 HDMI 2.1 TX Compliance Testing with AEQ Enabled
      11. 8.2.11 HDMI 2.1 Link Training Compatible Rx EQ
      12. 8.2.12 Input Signal Detect
      13. 8.2.13 Main Link Outputs
        1. 8.2.13.1 Transmitter Bias
        2. 8.2.13.2 Transmitter Impedance Control
        3. 8.2.13.3 TX Slew Rate Control
        4. 8.2.13.4 TX Pre-Emphasis and De-Emphasis Control
        5. 8.2.13.5 TX Swing Control
      14. 8.2.14 DDC Buffer
      15. 8.2.15 HDMI DDC Capacitance
      16. 8.2.16 DisplayPort
    3. 8.3 Device Functional Modes
      1. 8.3.1 MODE Control
        1. 8.3.1.1 I2C Mode (MODE = "F")
        2. 8.3.1.2 Pin Strap Modes
          1. 8.3.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
          2. 8.3.1.2.2 Pin-Strap HDMI 2.1 Function (MODE = "0"): Fixed Rx EQ and DDC Buffer Enabled
          3. 8.3.1.2.3 Pin-Strap HDMI 2.1 Function (MODE = "1"): Flexible RX EQ and DDC Buffer Enabled
          4. 8.3.1.2.4 Pin-Strap HDMI 2.1 Function (MODE = "R"): Flexible Rx EQ and DDC Buffer Disabled
      2. 8.3.2 DDC Snoop Feature
        1. 8.3.2.1 HDMI Type
        2. 8.3.2.2 HDMI 2.1 FRL Snoop
      3. 8.3.3 Low Power States
    4. 8.4 Programming
      1. 8.4.1 Pseudocode Examples
        1. 8.4.1.1 HDMI 2.1 Source Example with DDC Snoop and DDC Buffer Enabled
        2. 8.4.1.2 HDMI 2.1 Source Example with DDC Snoop Disabled and DDC Buffer Disabled
      2. 8.4.2 TDP1204 I2C Address Options
      3. 8.4.3 I2C Target Behavior
    5. 8.5 Register Maps
      1. 8.5.1 TDP1204 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Source-Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pre-Channel (LAB)
        2. 9.2.2.2 Post-Channel (LCD)
        3. 9.2.2.3 Common Mode Choke
        4. 9.2.2.4 ESD Protection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Sink-Side Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedures
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Supply Decoupling
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントのサポート
      1. 10.1.1 関連資料
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.13.2 Transmitter Impedance Control

HDMI 2.0 standards require a source termination impedance approximately 100-Ω for data rates > 3.4-Gbps. HDMI 1.4b requires no source termination but has a provision for termination for higher data rates greater than 1.65-Gbps. Enabling this termination is optional. Table 8-13 lists how the TDP1204 terminations are controlled automatically when in pin strap mode. Depending on the MODE pin, the CFG0 pin can be used to select the HDMI 1.4 termination between open and 300-Ω.

The TDP1204 supports automatic selection between open and 300-Ω termination when operating in HDMI 1.4. In pin-strap mode with CTL0 low, the TDP1204 will enable open termination when HDMI clock frequency is less than fHDMI14_open and will enable 300-Ω termination when HDMI clock frequency is greater than fHDMI14_300. TXTERM_AUTO_HDMI14 register controls this feature in I2C mode.

In I2C mode, termination is controlled through the registers as provided in Table 8-12.

Table 8-12 Source Termination Control in I2C mode
TX_AC_EN Register TERM Register TXTERM_AUTO_HDMI14 Register Source Termination
0 00 X None
0 01 X Parallel ≅ 300-Ω across P and N
0 10 X Automatic. HDMI 2.0 or HDM 2.1. parallel ≅ 100-Ω across P and N
0 10 1 Automatic. HDMI 1.4. parallel ≅ 300-Ω across P and N
0 10 0 Automatic. HDMI 1.4. No termination if HDMI clock frequency is ≤ fHDMI14_open.
0 10 0 Automatic. HDMI 1.4. Parallel ≅ 300-Ω across P and N termination if HDMI clock frequency is ≥ fHDMI14_300.
0 11 X Parallel ≈ 100-Ω across P and N
1 00 X ≅ 150-Ω to supply (VCC) on both P and N
1 01 X ≅ 150-Ω to supply (VCC) on both P and N
1 10 X Automatic. ≅ 150-Ω to supply (VCC) on both P and N for HDMI 1.4. Otherwise ≅ 50-Ω to supply (VCC) on both P and N.
1 11 X ≅ 50-Ω to supply (VCC) on both P and N
Table 8-13 Automatic Source Termination Control in Pin-Strap Mode
HDMI ModeAC_EN pinSource Termination
HDMI 1.40None or parallel ≅ 300-Ω across P and N depending on state of SCL/CFG0 pin
HDMI 2.00Parallel ≅ 100-Ω across P and N
HDMI 1.41≅ 150-Ω to supply (VCC) on both P and N
HDMI 2.01≅ 50-Ω to supply (VCC) on both P and N