SNLS766 July   2024 TDP20MB421

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High-Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 5-Level Control Inputs
      2. 6.3.2 Linear Equalization
      3. 6.3.3 Flat Gain
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP 2.1 Mainlink Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 DC Electrical Characteristics

over operating free-air temperature and voltage range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Power
PACTDevice active power All channels enabled (PD = L)720970mW
PSTBYDevice power consumption in standby power modeAll channels disabled (PD = H)2336mW
Control IO
VIHHigh level input voltageSDA, SCL, PD, SEL pins2.1V
VILLow level input voltageSDA, SCL, PD, SEL pins1.08V
VOHHigh level output voltageRpullup = 4.7kΩ (SDA, SCL pins)2.1V
VOLLow level output voltageIOL = –4mA (SDA, SCL pins)0.4V
IIH,SELInput high leakage current for SEL pinsVInput =  VCC, for SEL pin100µA
IIHInput high leakage currentVInput = VCC (SCL, SDA, PD pins)10µA
IILInput low leakage currentVInput = 0V (SCL, SDA, PD, SEL pins)–10µA
IIH,FSInput high leakage current for fail safe input pinsVInput = 3.6V, VCC = 0V (SCL, SDA, PD, SEL pins)200µA
CIN-CTRLInput capacitanceSCL, SDA, PD, SEL pins1.6pF
5 Level IOs (MODE, GAIN, EQ1, EQ0, pins)
IIH_5LInput high leakage current, 5 level IOsVIN = 2.5V10µA
IIL_5LInput low leakage current for all 5 level IOs except MODEVIN = GND–10µA
IIL_5L,MODEInput low leakage current for MODE pinVIN = GND–200µA
Receiver
VRX-DC-CMRX DC common-mode voltageDevice is in an active or standby state1.4V
ZRX-DCRx DC single-ended impedance50Ω
ZRX-HIGH-IMP-DC-POSDC input CM input impedance during Reset or power-downInputs are at VRX-DC-CM voltage20kΩ
Transmitter
ZTX-DIFF-DCDC differential Tx impedanceImpedance of Tx during active signaling, VID, diff = 1Vpp100Ω
VTX-DC-CMTx DC common-mode voltage1.0V
ITX-SHORTTx short-circuit currentTotal current the Tx supplies when shorted to GND70mA