JAJSO92B November   2012  – March 2022 TFP401A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Digital I/O Electrical Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 7.3.2 TFP401A-Q1 Clocking and Data Synchronization
      3. 7.3.3 TFP401A-Q1 TMDS Input Levels and Input Impedance Matching
      4. 7.3.4 TFP401A-Q1 Device Incorporates HSYNC Jitter Immunity
    4. 7.4 Device Functional Modes
      1. 7.4.1 TFP401A-Q1 Modes of Operation
      2. 7.4.2 TFP401A-Q1 Output Driver Configurations
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
          1. 8.1.1.2.1 Data and Control Signals
          2. 8.1.1.2.2 Configuration Options
          3. 8.1.1.2.3 Power Supplies Decoupling
        3. 8.1.1.3 Application Curves
        4. 8.1.1.4 DVDD
        5. 8.1.1.5 OVDD
        6. 8.1.1.6 AVDD
        7. 8.1.1.7 PVDD
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Layer Stack
        2. 8.3.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      2. 8.3.2 Layout Example
      3. 8.3.3 TI PowerPAD 100-TQFP Package
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Timing Requirements

PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tpsAnalog input intra-pair (+ to –) differential skew (2)0.4tbit(1)
tccsAnalog input inter-pair or channel-to-channel skew (2)1tpix(3)
tijitWorst-case differential input-clock jitter tolerance(2)(4)50ps
tf1Fall time of data and control signals(5)(6)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tr1Rise time of data and control signals(5)(6)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tr2Rise time of ODCK clock(5)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tf2Fall time of ODCK clock(5)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tsu1Setup time, data and control signal to falling edge of ODCK1 pixel per clock, PIXS = low, OCK_INV = low1.8ns
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = low		3.8
2 pixels and STAG, PIXS = high, STAG = low, OCK_INV = low0.6
th1Hold time, data and control signal to falling edge of ODCK1 pixel per clock, PIXS = low, OCK_INV = low0.6ns
2 pixels and STAG, PIXS = high,
STAG = low, OCK_INV = low		2.5
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = low		2.9
tsu2Setup time, data and control signal to rising edge of ODCK1 pixels per clock, PIXS = low,
OCK_INV = high		2.1ns
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = high		4
2 pixels and STAG, PIXS = high,
STAG = low, OCK_INV = high		1.5
th2Hold time, data and control signal to rising edge of ODCK1 pixel per clock, PIXS = low, OCK_INV = high0.3ns
2 pixels and STAG, PIXS = high,
STAG = low, OCK_INV = high		2.4
2 pixels per clock, PIXS = high,
STAG = high, OCK_INV = high		2.1
tpixPixel time(3)6.0640ns
(1) tbit is 1/10 the pixel time, tpix.
(2) Specified by characterization.
(3) tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK, is equal to tpix when in 1-pixel-per-clock mode or 2 tpix when in 2-pixels-per-clock mode.
(4) Measured differentially at 50% crossing using ODCK output clock as trigger.
(5) Rise and fall times measured as time between 20% and 80% of signal amplitude.
(6) Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1].
(7) Amount of time detected between DE transitions determines whether link is active or inactive. SCDT indicates link activity.
GUID-53690A82-7676-4041-95E2-812E0311C56C-low.gifFigure 6-1 Rise and Fall Times of Data and Control Signals
GUID-8FD1D8FD-5F49-4CB1-A883-16C7A4B2861A-low.gifFigure 6-2 Rise and Fall Times of ODCK
GUID-46984A95-8A9F-4C3A-B1DB-6C38C2BE0EB6-low.gifFigure 6-3 ODCK Frequency
GUID-6B0F8C2E-3BCF-4251-85FF-A33EDD39710E-low.gifFigure 6-4 Data Setup and Hold Times to Rising and Falling Edges of ODCK
GUID-DA37585F-0460-4604-982E-05A97D64DFE3-low.gifFigure 6-5 ODCK High to QE[23:0] Staggered Data Output
GUID-15AD9161-3932-4BCF-9B12-AC83860A9615-low.gifFigure 6-6 Delay From PD Low to Hi-Z Outputs
GUID-0B77F62F-EEB6-4C99-AB87-EB863AA719DB-low.gifFigure 6-7 Delay From PDO Low to Hi-Z Outputs
GUID-44484C50-BD1A-4567-A22B-2F5684FC06C6-low.gifFigure 6-8 Delay From PD Low to High Until Inputs Are Active
GUID-86533586-68BD-46D5-8140-750E5A158FD8-low.gifFigure 6-9 Time From DE Transitions to SCDT Low and SCDT High