JAJSO92B
November 2012 – March 2022
TFP401A-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
DC Digital I/O Electrical Characteristics
6.6
DC Electrical Characteristics
6.7
AC Electrical Characteristics
6.8
Timing Requirements
6.9
Switching Characteristics
6.10
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
TMDS Pixel Data and Control Signal Encoding
7.3.2
TFP401A-Q1 Clocking and Data Synchronization
7.3.3
TFP401A-Q1 TMDS Input Levels and Input Impedance Matching
7.3.4
TFP401A-Q1 Device Incorporates HSYNC Jitter Immunity
7.4
Device Functional Modes
7.4.1
TFP401A-Q1 Modes of Operation
7.4.2
TFP401A-Q1 Output Driver Configurations
8
Application and Implementation
8.1
Application Information
8.1.1
Typical Application
8.1.1.1
Design Requirements
8.1.1.2
Detailed Design Procedure
8.1.1.2.1
Data and Control Signals
8.1.1.2.2
Configuration Options
8.1.1.2.3
Power Supplies Decoupling
8.1.1.3
Application Curves
8.1.1.4
DVDD
8.1.1.5
OVDD
8.1.1.6
AVDD
8.1.1.7
PVDD
8.2
Power Supply Recommendations
8.3
Layout
8.3.1
Layout Guidelines
8.3.1.1
Layer Stack
8.3.1.2
Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
8.3.2
Layout Example
8.3.3
TI PowerPAD 100-TQFP Package
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
サポート・リソース
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PZP|100
MPQF053D
サーマルパッド・メカニカル・データ
PZP|100
PPTD033I
発注情報
jajso92b_oa
jajso92b_pm
7.4
Device Functional Modes