JAJST56D October 2001 – February 2024 TFP410
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VLOW | MSEL[3:1] | TSEL | RSEN | HTPLG | MDI |
Bit | Field | Type | Description |
---|---|---|---|
7 | VLOW | R/W | This read only register indicates the VREF input level. 0: This bit is a logic level (0) if the VREF analog input selects high-swing inputs 1: This bit is a logic level (1) if the VREF analog input selects low-swing inputs |
6:4 | MSEL[3:1] | R/W | This read/write register contains the source select of the monitor sense output pin. 000: Disabled. MSEN output high 001: Outputs the MDI bit (interrupt) 010: Outputs the RSEN bit (receiver detect) 011: Outputs the HTPLG bit (hot plug detect) |
3 | TSEL | R/W | This read/write register contains the interrupt generation source select. 0: Interrupt bit (MDI) is generated by monitoring RSEN 1: Interrupt bit (MDI) is generated by monitoring HTPLG |
2 | RSEN | R/W | This read only register contains the receiver sense input logic state, which is valid only for dc-coupled systems. 0: A powered-on receiver is not detected 1: A powered-on receiver is detected (that is, connected to the DVI transmitter outputs) |
1 | HTPLG | R/W | This read only register contains the hot plug detection input logic state. 0: Logic level detected on the EDGE/HTPLG pin (pin 9) 1: High level detected on the EDGE/HTPLG pin (pin 9) |
0 | MDI | R/W | This read/write register contains the monitor detect interrupt mode. 0: Detected logic level change in detection signal (to clear, write one to this bit) 1: Logic level remains the same |