The I²C interface is used to access the internal TFP410 registers. This two-pin interface consists of the SCL clock line and the SDA serial data line. The basic I²C access cycles are shown in Figure 6-5 and Figure 6-6.

Figure 6-5 I²C Start and Stop Conditions

The basic access write cycle consists of the following:

1. A start condition
2. A target address cycle
3. A sub-address cycle
4. Any number of data cycles
5. A stop condition

The basic access read cycle consists of the following:

1. A start condition
2. A target write address cycle
3. A sub-address cycle
4. A restart condition
5. A target read address cycle
6. Any number of data cycles
7. A stop condition

The start and stop conditions are shown in Figure 6-5. The high to low transition of SDA while SCL is high defines the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle, data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving device. Thus, each data/address cycle contains 9 bits as shown in Figure 6-6.

Figure 6-6 I²C Access Cycles

Following a start condition, each I²C device decodes the target address. The TFP410 responds with an acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address. During subsequent sub-address and data cycles, the TFP410 responds with acknowledge as shown in Figure 6-7. The sub-address is auto-incremented after each data cycle.

The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device may drive the SDA signal low. The controller indicates a not acknowledge condition ( A) by keeping the SDA signal high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 6-8.

The target address consists of 7 bits of address along with 1 bit of read/write information (read = 1, write = 0) as shown below in Figure 6-6 and Figure 6-7. For the TFP410, the selectable target addresses (including the R/W bit) using A[3:1] are 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, and 0x7E for write cycles and 0x71, 0x73, 0x75, 0x77, 0x79, 0x7B, 0x7D, and 0x7F for read cycles.

Figure 6-7 I²C Write Cycle

Figure 6-8 I²C Read Cycle