JAJSI65C November   2015  – October 2024 THS4541-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: (Vs+) – Vs– = 5 V
    6. 6.6 Electrical Characteristics: (Vs+) – Vs– = 3 V
    7. 6.7 Typical Characteristics: 5-V Single Supply
    8. 6.8 Typical Characteristics: 3-V Single Supply
    9. 6.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 7 Parameter Measurement Information
    1. 7.1 Example Characterization Circuits
    2. 7.2 Frequency-Response Shape Factors
    3. 7.3 I/O Headroom Considerations
    4. 7.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 7.5 Noise Analysis
    6. 7.6 Factors Influencing Harmonic Distortion
    7. 7.7 Driving Capacitive Loads
    8. 7.8 Thermal Analysis
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Terminology and Application Assumptions
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Differential I/O
      2. 8.3.2 Power-Down Control Pin ( PD)
        1. 8.3.2.1 Operating the Power Shutdown Feature
      3. 8.3.3 Input Overdrive Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 8.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 8.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 8.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 8.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 8.4.2 Differential-Input to Differential-Output Operation
        1. 8.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 8.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Designing Attenuators
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Interfacing to High-Performance ADCs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 TINA Simulation Model Features
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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発注情報

6.6 Electrical Characteristics: (Vs+) – Vs– = 3 V

at TA ≈ 25°C, Vocm = open (defaults midsupply), Vout = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs (unless otherwise noted); see Figure 7-1 for an ac-coupled gain of a 2-V/V test circuit, and Figure 7-3 for a dc-coupled gain of a 2-V/V test circuit
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST
LEVEL(1)
AC PERFORMANCE
Small-signal bandwidthVout = 100 mVPP, G = 1600MHzC
Vout = 100 mVPP, G = 2 (see Figure 7-1)500C
Vout = 100 mVPP, G = 5200C
Vout = 100 mVPP, G = 10120C
Gain-bandwidth productVout = 100 mVPP, G = 20850MHzC
Large-signal bandwidthVout = 2 VPP, G = 2 (see Figure 7-1)300MHzC
Bandwidth for 0.1-dB flatnessVout = 2 VPP, G = 2 (see Figure 7-1)90MHzC
Slew rate(2)Vout = 2-V step, FPBW (see Figure 7-1)1300V/µsC
Rise/fall timeVout = 2-V step, G = 2, input ≤ 0.3 ns tr
(see Figure 7-3)		1.8nsC
Settling timeTo 1%, Vout = 2-V step, tr = 2 ns, G = 2
(see Figure 7-3)		5nsC
To 0.1%, Vout = 2-V step, tr = 2 ns, G = 2
(see Figure 7-3)		8C
Overshoot and undershootVout = 2-V step G = 2, input ≤ 0.3 ns tr
(see Figure 7-3)		10%C
100-kHz harmonic distortionVout = 2 VPP, G = 2, HD2 (see Figure 7-1)–140dBcC
Vout = 2 VPP, G = 2, HD3 (see Figure 7-1)–140C
10-MHz harmonic distortionVout = 2 VPP, G = 2, HD2 (see Figure 7-1)–92dBcC
Vout = 2 VPP, G = 2, HD3 (see Figure 7-1)–89C
2nd-order intermodulation distortionf = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 7-1)		–89dBcC
3rd-order intermodulation distortionf = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 7-1)		–87dBcC
Input voltage noisef > 100 kHz2.2nV/√HzC
Input current noisef > 1 MHz1.9pA/√HzC
Overdrive recovery time2X output overdrive, either polarity20nsC
Closed-loop output impedancef = 10 MHz (differential)0.1ΩC
DC PERFORMANCE
AOLOpen-loop voltage gain100119dBA
Input-referred offset voltageTA = 25°C–450±100400µVA
TA = 0°C to 70°C–600±100600B
TA = –40°C to +85°C–700±100700B
TA = –40°C to +125°C–850±100850B
Input offset voltage drift(3)TA = –40°C to +125°C–2.4±0.52.4µV/°CB
Input bias current
(positive out of node)		TA = 25°C912µAA
TA = 0°C to 70°C912.5B
TA = –40°C to +85°C913B
TA = –40°C to +125°C913.5B
Input bias current drift(3)TA = –40°C to +125°C–515nA/°CB
Input offset currentTA = 25°C–500±150500nAA
TA = 0°C to 70°C–550±150550B
TA = –40°C to +85°C–580±150580B
TA = –40°C to +125°C–620±150620B
Input offset current drift(3)TA = –40°C to +125°C–1.3±0.31.3nA/°CB
INPUT
Common-mode input low< 3-dB degradation in CMRR from midsupplyTA = 25°C(Vs–) – 0.2(Vs–) – 0.1VA
TA = –40°C to +125°C(Vs–) – 0.1Vs–B
Common-mode input high< 3-dB degradation in CMRR from midsupplyTA = 25°C(Vs+) – 1.3(Vs+) –1.2VA
TA = –40°C to +125°C(Vs+) – 1.3B
Common-mode rejection ratioInput pins at ((Vs+) – Vs–) / 285100dBA
Input impedance differential modeInput pins at ((Vs+) – Vs–) / 2110 || 0.85kΩ || pFC
OUTPUT
Output voltage lowTA = 25°C(Vs–) + 0.2(Vs–) + 0.25VA
TA = –40°C to +125°C(Vs–) + 0.2(Vs–) + 0.25B
Output voltage highTA = 25°C(Vs+) – 0.25(Vs+) – 0.2VA
TA = –40°C to +125°C(Vs+) – 0.25(Vs+) – 0.2B
Output current driveTA = 25°C±55±60mAA
TA = –40°C to +125°C±55B
POWER SUPPLY
Specified operating voltage2.735.4VB
Quiescent operating currentTA = 25°C, Vs+ = 3 V9.39.710.1mAA
TA = –40°C to +125°C99.710.6B
±PSRRPower-supply rejection ratioEither supply pin to differential Vout85100dBA
POWER DOWN
Enable voltage threshold(Vs–) + 1.7VA
Disable voltage threshold(Vs–) + 0.7VA
Disable pin bias currentPD = Vs– → Vs+2050nAB
Power-down quiescent currentPD = (Vs–) + 0.7 V230µAA
PD = Vs–1.08.0A
Turn-on time delayTime from PD = low to Vout = 90% of final value100nsC
Turn-off time delayTime from PD = low to Vout = 10% of final value60nsC
OUTPUT COMMON-MODE VOLTAGE CONTROL(4)
Small-signal bandwidthVocm = 100 mVPP140MHzC
Slew rate(2)Vocm = 1-V step350V/µsC
Gain0.9750.9870.990V/VA
Input bias currentConsidered positive out of node–0.70.10.7µAA
Input impedanceVocm input driven to ((Vs+) – Vs–) / 247 || 1.2kΩ || pFC
Default voltage offset from
((Vs+) – Vs–) / 2		Vocm pin open–40±1040mVA
CM VosCommon-mode offset voltageVocm input driven to ((Vs+) – Vs–) / 2TA = 25°C–5±25mVA
TA = 0°C to 70°C–5.8±25.8B
TA = –40°C to +85°C–6.2±26.2B
TA = –40°C to +125°C–7±27B
Common-mode offset voltage drift(3)Vocm input driven to ((Vs+) – Vs–) / 2–20±420µV/°CB
Common-mode loop supply headroom to negative supply< ±12-mV shift from midsupply CM VosTA = 25°C0.88VA
TA = 0°C to 70°C0.91B
TA = –40°C to +85°C0.94B
TA = –40°C to +125°C0.94B
Common-mode loop supply headroom to positive supply< ±12-mV shift from midsupply CM VosTA = 25°C1.1VA
TA = 0°C to 70°C1.15B
TA = –40°C to +85°C1.2B
TA = –40°C to +125°C1.2B
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) × 2π × f–3dB.
(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
(4) Specifications are from input Vocm pin to differential output average voltage.