JAJSI65 データシート

JAJSI65C November 2015 – October 2024 THS4541-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGT|16
- MPQF119H

サーマルパッド・メカニカル・データ

RGT|16
- QFND571B

発注情報

6.5 Electrical Characteristics: (Vs+) – Vs– = 5 V

at T_A ≈ 25°C, Vocm = open (defaults midsupply), Vout = 2 V_PP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V, single-ended input, differential output, and PD = +Vs (unless otherwise noted); see Figure 7-1 for an ac-coupled gain of a 2-V/V test circuit, and Figure 7-3 for a dc-coupled gain of a 2-V/V test circuit

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT	TEST LEVEL⁽¹⁾
AC PERFORMANCE
	Small-signal bandwidth	Vout = 100 mV_PP, G = 1			620		MHz	C
		Vout = 100 mV_PP, G = 2 (see Figure 7-1)			500			C
		Vout = 100 mV_PP, G = 5			210			C
		Vout = 100 mV_PP, G = 10			125			C
	Gain-bandwidth product	Vout = 100 mV_PP, G = 20			850		MHz	C
	Large-signal bandwidth	Vout = 2 V_PP, G = 2 (see Figure 7-1)			340		MHz	C
	Bandwidth for 0.1-dB flatness	Vout = 2 V_PP, G = 2 (see Figure 7-1)			100		MHz	C
	Slew rate⁽²⁾	Vout = 2-V_PP, FPBW (see Figure 7-1)			1500		V/µs	C
	Rise/fall time	Vout = 2-V step, G = 2 input ≤ 0.3 ns t_r (see Figure 7-3)			1.4		ns	C
	Settling time	To 1%, Vout = 2-V step, t_r = 2 ns, G = 2 (seeFigure 7-3)			4		ns	C
	Settling time	To 0.1%,Vout = 2-V step, t_r = 2 ns, G = 2 (see Figure 7-3)			8		ns	C
	Overshoot and undershoot	Vout = 2-V step G = 2, input ≤ 0.3 ns t_r (see Figure 7-3)			10%			C
	100-kHz harmonic distortion	Vout = 2 V_PP, G = 2, HD2 (see Figure 7-1)			–140		dBc	C
	100-kHz harmonic distortion	Vout = 2 V_PP, G = 2, HD3 (see Figure 7-1)			–140		dBc	C
	10-MHz harmonic distortion	Vout = 2 V_PP, G = 2, HD2 (see Figure 7-1)			–95		dBc	C
	10-MHz harmonic distortion	Vout = 2 V_PP, G = 2, HD3 (see Figure 7-1)			–90		dBc	C
	2nd-order intermodulation distortion	f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 V_PP (1 V_PP per tone) (see Figure 7-1)			–90		dBc	C
	3rd-order intermodulation distortion	f = 10 MHz, 100-kHz tone spacing, Vout envelope = 2 V_PP (1 V_PP per tone) (see Figure 7-1)			–85		dBc	C
	Input voltage noise	f > 100 kHz			2.2		nV/√Hz	C
	Input current noise	f > 1 MHz			1.9		pA/√Hz	C
	Overdrive recovery time	2 × output overdrive, either polarity			20		ns	C
	Closed-loop output impedance	f = 10 MHz (differential)			0.1		Ω	C
DC PERFORMANCE
A_OL	Open-loop voltage gain			100	119		dB	A
	Input-referred offset voltage	T_A = 25°C		–450	±100	450	µV	A
		T_A = 0°C to 70°C		–600	±100	600		B
		T_A = –40°C to +85°C		–700	±100	700		B
		T_A = –40°C to +125°C		–850	±100	850		B
	Input offset voltage drift⁽³⁾	T_A = –40°C to +125°C		–2.4	±0.5	2.4	µV/°C	B
	Input bias current (positive out of node)	T_A = 25°C			10	13	µA	A
		T_A = 0°C to 70°C			11	13.5		B
		T_A = –40°C to +85°C			12	14		B
		T_A = –40°C to +125°C			12	14.5		B
	Input bias current drift⁽³⁾	T_A = –40°C to +125°C			6	15	nA/°C	B
	Input offset current	T_A = 25°C		–500	±150	500	nA	A
		T_A = 0°C to 70°C		–550	±150	550		B
		T_A = –40°C to +85°C		–580	±150	580		B
		T_A = –40°C to +125°C		–620	±150	620		B
	Input offset current drift⁽³⁾	T_A = –40°C to +125°C		–1.3	±0.3	1.3	nA/°C	B
INPUT
	Common-mode input low	< 3-dB degradation in CMRR from midsupply	T_A = 25°C		(Vs–) – 0.2	(Vs–) – 0.1	V	A
	Common-mode input low	< 3-dB degradation in CMRR from midsupply	T_A = –40°C to +125°C		(Vs–) – 0.1	Vs–	V	B
	Common-mode input high	< 3-dB degradation in CMRR from midsupply	T_A = 25°C	(Vs+) – 1.3	(Vs+) –1.2		V	A
	Common-mode input high	< 3-dB degradation in CMRR from midsupply	T_A = –40°C to +125°C	(Vs+) – 1.3			V	B
	Common-mode rejection ratio	Input pins at ((Vs+) – Vs–) / 2		85	100		dB	A
	Input impedance differential mode	Input pins at ((Vs+) – Vs–) / 2			110 \|\| 0.85		kΩ \|\| pF	C
OUTPUT
	Output voltage low	T_A = 25°C			(Vs–) + 0.2	(Vs–) + 0.25	V	A
	Output voltage low	T_A = –40°C to +125°C			(Vs–) + 0.2	(Vs–) + 0.25	V	B
	Output voltage high	T_A = 25°C		(Vs+) – 0.25	(Vs+) – 0.2		V	A
	Output voltage high	T_A = –40°C to +125°C		(Vs+) – 0.25	(Vs+) – 0.2		V	B
	Output current drive	T_A = 25°C		±75	±100		mA	A
	Output current drive	T_A = –40°C to +125°C		±75			mA	B
POWER SUPPLY
	Specified operating voltage			2.7	5	5.4	V	B
	Quiescent operating current	T_A = 25°C, Vs+ = 5 V		9.7	10.1	10.5	mA	A
	Quiescent operating current	T_A = –40°C to +125°C		9.4	10.1	11	mA	B
±PSRR	Power-supply rejection ratio	Either supply pin to differential Vout		85	100		dB	A
POWER DOWN
	Enable voltage threshold			(Vs–) + 1.7			V	A
	Disable voltage threshold					(Vs–) + 0.7	V	A
	Disable pin bias current	PD = Vs– → Vs+			20	50	nA	B
	Power-down quiescent current	PD = (Vs–) + 0.7 V			6	30	µA	A
	Power-down quiescent current	PD = Vs–			2	8	µA	A
	Turn-on time delay	Time from PD = low to Vout = 90% of final value			100		ns	C
	Turn-off time delay	Time from PD = low to Vout = 10% of final value			60		ns	C
OUTPUT COMMON-MODE VOLTAGE CONTROL⁽⁴⁾
	Small-signal bandwidth	Vocm = 100 mV_PP			150		MHz	C
	Slew rate⁽²⁾	Vocm = 2-V step			400		V/µs	C
	Gain			0.975	0.982	0.995	V/V	A
	Input bias current	Considered positive out of node		–0.7	0.1	0.7	µA	A
	Input impedance	Vocm input driven to ((Vs+) – Vs–) / 2			47 \|\| 1.2		kΩ \|\| pF	C
	Default voltage offset from ((Vs+) – Vs–) / 2	Vocm pin open		–40	±8	40	mV	A
CM Vos	Common-mode offset voltage	Vocm input driven to ((Vs+) – Vs–) / 2	T_A = 25°C	–5	±2	5	mV	A
			T_A = 0°C to 70°C	–6	±2	5.8		B
			T_A = –40°C to +85°C	–6.2	±2	6.2		B
			T_A = –40°C to +125°C	–7	±2	7.08		B
	Common-mode offset voltage drift⁽³⁾	Vocm input driven to ((Vs+) – Vs–) / 2		–20	±4	+20	µV/°C	B
	Common-mode loop supply headroom to negative supply	< ±12-mV shift from midsupply CM Vos	T_A = 25°C	0.88			V	A
			T_A = 0°C to 70°C	0.91				B
			T_A = –40°C to +85°C	0.94				B
			T_A = –40°C to +125°C	0.94				B
	Common-mode loop supply headroom to positive supply	< ±12-mV shift from midsupply CM Vos	T_A = 25°C	1.1			V	A
			T_A = 0°C to 70°C	1.15				B
			T_A = –40°C to +85°C	1.2				B
			T_A = –40°C to +125°C	1.2				B

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A ≈ 25°C; over temperature limits by characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.

(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (V_P / √2) × 2π × f_–3dB.

(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.

(4) Specifications are from the input Vocm pin to the differential output average voltage.