8.1 Video vs Computer Graphics Application

THS8200 is a highly integrated and flexible universal analog component video/graphics generator that can be used in any application requiring D/A conversion of video/graphics signals.

In a typical video application (for example, DVD player, set-top box), the THS8200 receives its input from an MPEG decoder or media processor engine and converts the signal into the analog domain, thereby generating the correct timing/frame format for the selected format.

Its ITU-R.BT656 output port could be used to connect to an NTSC/PAL video encoder, such as the Texas Instruments TVP6000, for regular composite/S-video output.

Note that because the DAC speed is rated up to 205 MSPS, all popular SDTV and HDTV formats, including 1080I and 720P, are supported in both 1x and 2x interpolated modes. The 1080P is supported at the 1x rate.

Figure 8-1 Typical Video Application

Because of its programmable Hsync/Vsync outputs, the on-chip support for RGB as well as YCbCr color spaces and its internal color space conversion circuit, and the DAC operational speed of 205 MSPS, all PC graphics formats are supported as well, up to UXGA at 75 Hz. Video interpolation is now bypassed so that the full 205 MSPS can be used for the 1x pixel clock.

Figure 8-2 Computer Graphics Application

8.2 DVI to Analog YPbPr/RGB Application

Together with a DVI receiver, this device forms a two-chip solution to convert video or graphics formats sent over a DVI interface to an analog RGB or YPbPr format using embedded composite sync or separate Hsync, Vsync. THS8200 connects gluelessly to a DVI receiver using its data input bus and HS_IN and VS_IN terminals. TI DVI 1.0 (with HDCP) receivers provide a data enable (DE) signal that is high during the active video window. The THS8200 can be configured to interpret this DE signal on its FID terminal to automatically insert a user-programmable blanking-level amplitude outside the active video window on its analog outputs; this blanking level can be correctly positioned for either RGB or YPbPr analog outputs. The user can optionally perform color space conversion in the THS8200 and adjust offset and gain ranges through the device's CSM block.

When sending (interlaced) video over DVI, the EIA-861 specification describes a method to derive the fieldID signal—not directly available from a DVI1.0 (with HDCP) receiver—from the relative alignment of the Hsync and Vsync signals. The THS8200 can be configured to derive internally the correct even/odd field identification from Hsync/Vsync alignment according to this specification, instead of using the FieldID signal on its FID input terminal. This avoids the need for additional glue logic in a DVI application.

8.3 Master vs Slave Timing Modes

In slave timing mode, the THS8200 output display timing is synchronized to the video data source. Display timing output signals are based on input sync signals, either fed to the device on the dedicated Hsync, Vsync, and FieldID (HS_IN, VS_IN, and FID) input terminals or based on SAV/EAV codes embedded in the input video data.

Figure 8-3 Slave Operation Mode of THS8200

In master timing mode, the THS8200 generates two sets of output synchronization signals.

• HS_IN and VS_IN now become output signals to the video source (FID unused).
• HS_OUT and VS_OUT are still output signals to display device.

The intended purpose is that THS8200 requests video data from a source that requires external timing, such as video memory.

Figure 8-4 Master Operation Mode of THS8200