SLES032E June   2002  – September 2014 THS8200

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Terminal Configuration and Functions
    1. 3.1 Terminal Functions
  4. 4 Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  Handling Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
    5. 4.5  Power Supply
    6. 4.6  Digital Inputs, DC Characteristics
    7. 4.7  Analog (DAC) Outputs
    8. 4.8  Nonlinearity
      1. 4.8.1 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV Without Bias
      2. 4.8.2 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 700 mV + 350-mV Bias
      3. 4.8.3 Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) for 1.25 V Without Bias
    9. 4.9  Analog Output Bandwidth (sinx/x corrected) at fS = 205 MSPS
    10. 4.10 Output Compliance vs Full-Scale Adjustment Resistor Value
    11. 4.11 Vertical Sync of the HDTV 1080I Format Preset in First and Second Field, and Horizontal Line Waveform Detail
  5. 5 Functional Overview
    1. 5.1 Data Manager (DMAN)
      1. 5.1.1  Interpolating Finite Impulse Responses Filter (IFIR)
      2. 5.1.2  Color-Space Conversion (CSC)
      3. 5.1.3  Clip/Shift/Multiplier (CSM)
      4. 5.1.4  Digital Multiplexer (DIGMUX)
      5. 5.1.5  Display Timing Generator (DTG)
      6. 5.1.6  Clock Generator (CGEN)
      7. 5.1.7  Clock Driver (CDRV)
      8. 5.1.8  I2C Host Interface (I2CSLAVE)
      9. 5.1.9  Test Block (TST)
      10. 5.1.10 D/A Converters (DACs)
  6. 6 Detailed Functional Description
    1. 6.1  Data Manager (DMAN)
    2. 6.2  Input Interface Formats
    3. 6.3  Clock Generator (CGEN)/Clock Driver (CDRV)
    4. 6.4  Color Space Conversion (CSC)
    5. 6.5  Clip/Shift/Multiplier (CSM)
      1. 6.5.1 Clipping
      2. 6.5.2 Shifting
      3. 6.5.3 Multiplying
    6. 6.6  Interpolating Finite Impulse Response Filter (IFIR)
    7. 6.7  Display Timing Generator (DTG)
      1. 6.7.1 Overview of Functionality
      2. 6.7.2 Functional Description
        1. 6.7.2.1 Predefined DTG Video Formats (Presets)
        2. 6.7.2.2 Internal Synchronization
        3. 6.7.2.3 Output Synchronization: Composite Sync
        4. 6.7.2.4 Output Synchronization: Hsync/Vsync Outputs
      3. 6.7.3 DTG Line Type Overview
        1. 6.7.3.1  HDTV Mode
        2. 6.7.3.2  Active Video
        3. 6.7.3.3  FULL NTSP (Full Normal Tri-Level Sync Pulse)
        4. 6.7.3.4  NTSP NTSP (Normal Tri-Level Sync Pulse/Normal Tri-Level Sync Pulse)
        5. 6.7.3.5  BTSP BTSP (Broad Pulse and Tri-Level Sync Pulse/Broad Pulse and Tri-Level Sync Pulse)
        6. 6.7.3.6  NTSP BTSP (Normal Tri-Level Sync Pulse/ Broad Pulse and Tri-Level Sync Pulse)
        7. 6.7.3.7  BTSP NTSP (Broad Pulse and Tri-Level Sync Pulse/Normal Tri-Level Sync Pulse)
        8. 6.7.3.8  Full BTSP (Full Broad Pulse and Tri-Level Sync Pulse)
        9. 6.7.3.9  SDTV Mode
        10. 6.7.3.10 NEQ_NEQ (Negative Equalization Pulse/Negative Equalization Pulse)
        11. 6.7.3.11 FULL_BSP (Full Broad Sync Pulse)
        12. 6.7.3.12 BSP_BSP (Broad Sync Pulse/Broad Sync Pulse)
        13. 6.7.3.13 FULL_NSP (Full Normal Sync Pulse)
        14. 6.7.3.14 NEQ_BSP (Negative Equalization Pulse/Broad Sync Pulse)
        15. 6.7.3.15 BSP_NEQ (Broad Sync Pulse/Negative Equalization Pulse)
        16. 6.7.3.16 FULL_NEQ (Full Negative Equalization Pulse)
        17. 6.7.3.17 NSP_ACTIVE (Normal Sync Pulse/Active Video)
        18. 6.7.3.18 ACTIVE_NEQ (Active Video/Negative Equalization Pulse)
        19. 6.7.3.19 ACTIVE VIDEO
    8. 6.8  D/A Conversion
      1. 6.8.1 RGB Output Without Sync Signal Insertion/General-Purpose Application DAC
      2. 6.8.2 SMPTE-Compatible RGB Output With Sync Signal Inserted on G (Green) Channel
      3. 6.8.3 SMPTE-Compatible Analog-Level Output With Sync Inserted on All RGB Channels
      4. 6.8.4 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on Y Channel Only
      5. 6.8.5 SMPTE-Compatible YPbPr Output With Sync Signal Inserted on All Channels
      6. 6.8.6 Summary of Supported Video Formats
    9. 6.9  Test Functions
    10. 6.10 Power Down
    11. 6.11 CGMS Insertion
    12. 6.12 I2C Interface
  7. 7 I2C Registers
    1. 7.1 I2C Register Map
    2. 7.2 Register Descriptions
      1. 7.2.1 System Control (Sub-Addresses 0x02−0x03)
      2. 7.2.2 Color Space Conversion Control (Sub-Addresses 0x04−0x19)
      3. 7.2.3 Test Control (Sub-Addresses 0x1A−0x1B)
      4. 7.2.4 Data Path Control (Sub-Address 0x1C)
      5. 7.2.5 Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D−0x3C)
      6. 7.2.6 DAC Control (Sub-Addresses 0x3D−0x40)
      7. 7.2.7 Clip/Shift/Multiplier Control (Sub-Addresses 0x41−0x4F)
      8. 7.2.8 Display Timing Generator Control, Part 2 (Sub-Addresses 0x50−0x82)
      9. 7.2.9 CGMS Control (Sub-Addresses 0x83−0x85)
    3. 7.3 THS8200 Preset Mode Line Type Definitions
      1. 7.3.1 SMPTE_274P (1080P)
      2. 7.3.2 274M Interlaced (1080I)
      3. 7.3.3 296M Progressive (720P)
      4. 7.3.4 SDTV 525 Interlaced Mode
      5. 7.3.5 SDTV 525 Progressive Mode
      6. 7.3.6 SDTV 625 Interlaced Mode
  8. 8 Application Information
    1. 8.1 Video vs Computer Graphics Application
    2. 8.2 DVI to Analog YPbPr/RGB Application
    3. 8.3 Master vs Slave Timing Modes
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Getting Started and Next Steps
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Community Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 I2C Registers

7.1 I2C Register Map

R/W registers can be written and read.

R registers are read-only.

Table 7-1 I2C Register Map

REGISTER NAME R/W SUB-ADDRESS BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0x00 Reserved
0x01
SYSTEM
version R 0x02 ver7 ver6 ver5 ver4 ver3 ver2 ver1 ver0
chip_ctl R/W 0x03 vesa_clk dll_bypass vesa_color bars dll_freq_
sel		 dac_pwdn chip_pwdn chip_ms arst_ func_n
COLOR SPACE CONVERSION
csc_r11 R/W 0x04 csc_ric1(5:0) csc_rfc1(9:8)
csc_r12 R/W 0x05 csc_rfc1(7:0)
csc_r21 R/W 0x06 csc_ric2(5:0) csc_rfc2(9:8)
csc_r22 R/W 0x07 csc_rfc2(7:0)
csc_r31 R/W 0x08 csc_ric3(5:0) csc_rfc3(9:8)
csc_r32 R/W 0x09 csc_rfc3(7:0)
csc_g11 R/W 0x0a csc_gic1(5:0) csc_gfc1(9:8)
csc_g12 R/W 0x0b csc_gfc1(7:0)
csc_g21 R/W 0x0c csc_gic2(5:0) csc_gfc2(9:8)
csc_g22 R/W 0x0d csc_gfc2(7:0)
csc_g31 R/W 0x0e csc_gic3(5:0) csc_gfc3(9:8)
csc_g32 R/W 0x0f csc_gfc3(7:0)
csc_b11 R/W 0x10 csc_bic1(5:0) csc_bfc1(9:8)
csc_b12 R/W 0x11 csc_bfc1(7:0)
csc_b21 R/W 0x12 csc_bic2(5:0) csc_bfc2(9:8)
csc_b22 R/W 0x13 csc_bfc2(7:0)
csc_b31 R/W 0x14 csc_bic3(5:0) csc_bfc3(9:8)
csc_b32 R/W 0x15 csc_bfc3(7:0)
csc_offs1 R/W 0x16 csc_offset1(9:2)
csc_offs12 R/W 0x17 csc_offset1(1:0) csc_offset2(9:4)
csc_offs23 R/W 0x18 csc_offset2(3:0) csc_offset3(9:6)
csc_offs3 R/W 0x19 csc_offset3(5:0) csc_
bypass		 c_uof_cnt l
TEST
tst_cntl1 R/W 0x1a st_
digbpass		 tst_offset Reserved
tst_cntl2 R/W 0x1b tst_ydelay(1:0) Reserved Reserved Reserved Reserved tst_ fastramp tst_ slowramp
DATA PATH
data_cntl R/W 0x1c data_
clk6 56_on		 data_fsadj data_ifir12 _bypass data_ifir35 _bypass data_
tristate656		 data_dman_cntl(2:0)
DISPLAY TIMING GENERATION, PART 1
dtg1_y_ sync1_lsb R/W 0x1d dtg1_y_blank(7:0)
dtg1_y_ sync2_lsb R/W 0x1e dtg1_y_sync_low(7:0)
dtg1_y_ sync3_lsb R/W 0x1f dtg1_y_sync_high(7:0)
dtg1_cbcr_ sync1_lsb R/W 0x20 dtg1_cbcr_blank(7:0)
dtg1_cbcr_ sync2_lsb R/W 0x21 dtg1_cbcr_sync_low(7:0)
dtg1_cbcr_ sync3_lsb R/W 0x22 dtg1_cbcr_sync_high(7:0)
dtg1_y_ sync_msb R/W 0x23 Reserved Reserved dtg1_y_blank(9:8) dtg1_y_sync_low(9:8) dtg1_y_sync_high(9:8)
dtg1_cbcr_ sync_msb R/W 0x24 Reserved Reserved dtg1_cbcr_blank(9:8) dtg1_cbcr_sync_low
(9:8 )		 dtg1_cbcr_ sync_high(9:8)
dtg1_spec_a R/W 0x25 dtg1_spec_a(7:0)
dtg1_spec_b R/W 0x26 dtg1_spec_b(7:0)
dtg1_spec_c R/W 0x27 dtg1_spec_c(7:0)
dtg1_spec_ d_lsb R/W 0x28 dtg1_spec_d(7:0)
dtg1_spec_ d1 R/W 0x29 dtg1_spec_d1(7:0)
dtg1_spec_ e_lsb R/W 0x2a dtg1_spec_e(7:0)
dtg1_spec_ deh_msb R/W 0x2b dtg1_
spe c_d(8)		 dtg1_spec _e(8) Reserved Reserved Reserved Reserved dtg1_spec_h(9:8)
dtg1_spec_ h_lsb R/W 0x2c dtg1_spec_h(7:0)
dtg1_spec_ i_msb R/W 0x2d Reserved Reserved Reserved Reserved dtg1_spec_i(11:8)
dtg1_spec_ i_lsb R/W 0x2e dtg1_spec_i(7:0)
dtg1_spec_ k_lsb R/W 0x2f dtg1_spec_k(7:0)
dtg1_spec_ k_msb R/W 0x30 Reserved Reserved Reserved Reserved Reserved dtg1_spec_k(10:8)
dtg1_spec_ k1 R/W 0x31 dtg1_spec_k1(7:0)
dtg1_spec_ g_lsb R/W 0x32 dtg1_spec_g(7:0)
dtg1_spec_ g_msb R/W 0x33 Reserved Reserved Reserved Reserved dtg1_spec_g(11:8)
dtg1_total_ pixels_msb R/W 0x34 Reserved Reserved Reserved dtg1_total_pixels(12:8)
dtg1_total_ pixels_lsb R/W 0x35 dtg1_total_pixels(7:0)
dtg1_fieldflip_ linecnt_ msb R/W 0x36 dtg1_field _flip Reserved Reserved Reserved Reserved dtg1_linecnt(10:8)
dtg1_ linecnt_lsb R/W 0x37 dtg1_linecnt(7:0)
dtg1_mode R/W 0x38 dtg1_on Reserved Reserved dtg1_pass _through dtg1_mode(3:0)
dtg1_frame_ field_size_msb R/W 0x39 Reserved dtg1_frame_size(10:8) Reserved dtg1_field_size(10:8)
dtg1_frame_ size_lsb R/W 0x3a dtg1_frame_size(7:0)
dtg1_field_ size_lsb R/W 0x3b dtg1_field_size(7:0)
dtg1_vesa_ cbar_size R/W 0x3c dtg1_vesa_cbar_size(7:0)
DAC
dac_cntl_msb R/W 0x3d Reserved dac_i2c_ cntl dac1_cntl(9:8) dac2_cntl(9:8) dac3_cntl(9:8)
dac1_cntl_lsb R/W 0x3e dac1_cntl(7:0)
dac2_cntl_lsb R/W 0x3f dac2_cntl(7:0)
dac3_cntl_lsb R/W 0x40 dac3_cntl(7:0)
CLIP/SHIFT/MULTIPLIER
csm_clip_ gy_low R/W 0x41 csm_clip_gy_low(7:0)
csm_clip_ bcb_low R/W 0x42 csm_clip_bcb_low(7:0)
csm_clip_ rcr_low R/W 0x43 csm_clip_rcr_low(7:0)
csm_clip_ gy_high R/W 0x44 csm_clip_gy_high(7:0)
csm_clip_ bcb_high R/W 0x45 csm_clip_bcb_high(7:0)
csm_clip_ rcr_high R/W 0x46 csm_clip_rcr_high(7:0)
csm_shift_gy R/W 0x47 csm_shift_gy(7:0)
csm_shift_bcb R/W 0x48 csm_shift_bcb(7:0)
csm_shift_rcr R/W 0x49 csm_shift_rcr(7:0)
csm_gy_ cntl_mult_ msb R/W 0x4a csm_mult _ gy_on csm_shift_ gy_on csm_gy_ high_clip_ on csm_gy_ low_clip_ on csm_of_ cntl csm_mult_gy(10:8)
csm_mult_ bcb_rcr_ msb R/W 0x4b Reserved csm_mult_bcb(10:8) Reserved csm_mult_rcr(10:8)
csm_mult_ gy_lsb R/W 0x4c csm_mult_gy(7:0)
csm_mult_ bcb_lsb R/W 0x4d csm_mult_bcb(7:0)
csm_mult_ rcr_lsb R/W 0x4e csm_mult_rcr(7:0)
csm_rcr_ bcb_cntl R/W 0x4f csm_mult _ rcr_on csm_mult_ bcb_on csm_shift_ rcr_on csm_shift_ bcb_on csm_rcr_ high_clip_ on csm_rcr_ low_clip_
on		 csm_bcb_ high_clip_ on csm_bcb _ low_clip_ on
DISPLAY TIMING GENERATION, PART 2
dtg2_bp1_ 2_msb R/W 0x50 Reserved dtg2_bp1(10:8) Reserved dtg2_bp2(10:8)
dtg2_bp3_ 4_msb R/W 0x51 Reserved dtg2_bp3(10:8) Reserved dtg2_bp4(10:8)
dtg2_bp5_ 6_msb R/W 0x52 Reserved dtg2_bp5(10:8) Reserved dtg2_bp6(10:8)
dtg2_bp7_ 8_msb R/W 0x53 Reserved dtg2_bp7(10:8) Reserved dtg2_bp8(10:8)
dtg2_bp9_ 10_msb R/W 0x54 Reserved dtg2_bp9(10:8) Reserved dtg2_bp10(10:8)
dtg2_bp11_ 12_msb R/W 0x55 Reserved dtg2_bp11(10:8) Reserved dtg2_bp12(10:8)
dtg2_bp13_ 14_msb R/W 0x56 Reserved dtg2_bp13(10:8) Reserved dtg2_bp14(10:8)
dtg2_bp15_ 16_msb R/W 0x57 Reserved dtg2_bp15(10:8) Reserved dtg2_bp16(10:8)
dtg2_bp1_lsb R/W 0x58 dtg2_bp1(7:0)
dtg2_bp2_lsb R/W 0x59 dtg2_bp2(7:0)
dtg2_bp3_lsb R/W 0x5a dtg2_bp3(7:0)
dtg2_bp4_lsb R/W 0x5b dtg2_bp4(7:0)
dtg2_bp5_lsb R/W 0x5c dtg2_bp5(7:0)
dtg2_bp6_lsb R/W 0x5d dtg2_bp6(7:0)
dtg2_bp7_lsb R/W 0x5e dtg2_bp7(7:0)
dtg2_bp8_lsb R/W 0x5f dtg2_bp8(7:0)
dtg2_bp9_lsb R/W 0x60 dtg2_bp9(7:0)
dtg2_bp10_ lsb R/W 0x61 dtg2_bp10(7:0)
dtg2_bp11_ lsb R/W 0x62 dtg2_bp11(7:0)
dtg2_bp12_ lsb R/W 0x63 dtg2_bp12(7:0)
dtg2_bp13_ lsb R/W 0x64 dtg2_bp13(7:0)
dtg2_bp14_ lsb R/W 0x65 dtg2_bp14(7:0)
dtg2_bp15_ lsb R/W 0x66 dtg2_bp15(7:0)
dtg2_bp16_ lsb R/W 0x67 dtg2_bp16(7:0)
dtg2_ linetype1 R/W 0x68 dtg2_linetype1(3:0) dtg2_linetype2(3:0)
dtg2_ linetype2 R/W 0x69 dtg2_linetype3(3:0) dtg2_linetype4(3:0)
dtg2_ linetype3 R/W 0x6a dtg2_linetype5(3:0) dtg2_linetype6(3:0)
dtg2_ linetype4 R/W 0x6b dtg2_linetype7(3:0) dtg2_linetype8(3:0)
dtg2_ linetype5 R/W 0x6c dtg2_linetype9(3:0) dtg2_linetype10(3:0)
dtg2_ linetype6 R/W 0x6d dtg2_linetype11(3:0) dtg2_linetype12(3:0)
dtg2_ linetype7 R/W 0x6e dtg2_linetype13(3:0) dtg2_linetype14(3:0)
dtg2_ linetype8 R/W 0x6f dtg2_linetype15(3:0) dtg2_linetype16(3:0)
dtg2_hlength_ lsb R/W 0x70 dtg2_hlength(7:0)
dtg2_ hlength_msb_ hdly_msb R/W 0x71 dtg2_hlength(9:8) Reserved dtg2_hdly(12:8)
dtg2_hdly_lsb R/W 0x72 dtg2_hdly(7:0)
dtg2_ vlength1_lsb R/W 0x73 dtg2_vlength1(7:0)
dtg2_ vlength1_msb_ vdly1_msb R/W 0x74 dtg2_vlength1(9:8) Reserved Reserved Reserved dtg2_vdly1(10:8)
dtg2_vdly1_lsb R/W 0x75 dtg2_vdly1(7:0)
dtg2_vlength2_ lsb R/W 0x76 dtg2_vlength2(7:0)
dtg2_ vlength2_msb_ vdly2_msb R/W 0x77 dtg2_vlength2(9:8) Reserved Reserved Reserved dtg2_vlength2(9:8)
dtg2_vdly2_lsb R/W 0x78 dtg2_vdly2(7:0)
dtg2_hs_ in_dly_msb R/W 0x79 Reserved Reserved Reserved dtg2_hs_in_dly(12:8)
dtg2_hs_ in_dly_lsb R/W 0x7a dtg2_hs_in_dly(7:0)
dtg2_vs_in_ dly_msb R/W 0x7b Reserved Reserved Reserved Reserved Reserved dtg2_vs_in_dly(10:8)
dtg2_vs_in_ dly_lsb R/W 0x7c dtg2_vs_in_dly(7:0)
dtg2_pixel_ cnt_msb R 0x7d dtg2_pixel_cnt(15:8)
dtg2_pixel_ cnt_lsb R 0x7e dtg2_pixel_cnt(7:0)
dtg2_line_ cnt_msb R 0x7f dtg2_ip_
fmt		 Reserved dtg2_line_cnt(10:8)
dtg2_line_ cnt_msb R 0x80 dtg2_line_cnt(7:0)
0x81 Reserved
dtg2_cntl R/W 0x82 dtg2_fid_ de_cntl dtg2_rgb_ mode_on dtg2_embedded_ timing dtg2_ vsout_pol dtg2_h sout_pol dtg2_fid_ pol dtg2_vs_ pol dtg2_hs_ pol
CGMS CONTROL
cgms_cntl_ header R/W 0x83 Reserved cgms_en cgms_header(5:0)
cgms_payload_ msb R/W 0x84 Reserved Reserved cgms_payload(13:8)
cgms_ payload_lsb R/W 0x85 cgms_payload(7:0)
misc_ppl_lsb R 0x86 misc_ppl(7:0)
misc_ppl_msb R 0x87 misc_ppl(7:0)
misc_lpf_lsb R 0x88 misc_lpf(7:0)
misc_lpf_msb R 0x89 misc_lpf(15:8)

7.2 Register Descriptions

Between { } are shown the name(s), subaddress(es) and bit position(s) where each register can be found in the register map.

The default register value is shown between [ ] in binary format, and hexadecimal (h) and/or decimal (d) notation where listed.

7.2.1 System Control (Sub-Addresses 0x02−0x03)

ver(7:0): Device version
{version 0x02(7..0)} [0000 0000]
The user can read this register to find out which version of THS8200 is in the system.
vesa_clk: Clock mode selection
{chip_ctl 0x03(7)} [0]
0 : Normal operation
1 : All clocks become identical, except for the half-rate clock, and the DLL is bypassed. This is used in VESA mode to support a direct 205-MHz input clock. No internal 2x interpolation is available. This mode should be used for all formats that require a >80 MSPS pixel clock because the internal DLL for 2x clock generation is specified only up to 80 MSPS.
The half-rate clock is still internally generated if needed to allow, for example, 148-MHz 20-bit input (1080P).
dll_bypass: DLL bypass
{chip_ctl 0x03(6)} [0]
0 : DLL used for clock generation; normal operation with internally generated 2x clock. This mode should be selected for most video formats when a 1x clock is available on the device clock input, and either 1x or 2x DAC operation is desired internally (as selected by register data_ifir35_bypass)
1 : DLL bypassed for clock generation. In this case the clock input on the CLKIN pin is used directly as the 2x clock, rather than the internally generated signal from the DLL.
vesa_colorbars: Color bar test pattern
{chip_ctl 0x03(5)} [0]
0 : normal operation
1 : Device generates color bar pattern; external video inputs are ignored. The color bar pattern is only supported in VESA PC graphics mode, with the device configured in master mode
(chip_ms = 1).
dll_freq_sel: dll_freq_sel:
{chip_ctl 0x03(4)} [0]
Sets a frequency range for the DLL 2x clock generation. The DLL should not be used at >80 MHz. In this case the vesa_clk register should be enabled. As a consequence, 2x video interpolation is not available for formats with >80 MHz pixel clock.
0 : high frequency range: pixel clock from 40−80 MHz
1 : low frequency range: pixel clock from 10−40 MHz
dac_pwdn: dac_pwdn:
{chip_ctl 0x03(3)} [0]
0 : normal operation
1 : DACs go into power-down state.
chip_pwdn: Chip power down
{chip_ctl 0x03(2)} [0]
0 : normal operation
1 : power down of all digital logic except I2C
chip_ms: Chip mode select
{chip_ctl 0x03(1)} [0]
0 : slave mode. Device synchronizes to incoming video sync signals, either embedded in ITU-R.BT656 interface or received from dedicated timing signals.
1 : master mode. Device requests video data and generates video input timing signals to external (memory) device, according to the programmed frame/field format. Master mode is only available when the DTG is operating in VESA mode (PC graphics signals).
arst_func_n: Chip software reset
{chip_ctl 0x03(0)} [1]
0 : functional block goes into reset state. I2C registers retain values.
Note: the user needs to issue a software reset after input video is disconnected from the input bus and reconnected (for example after a video format change), to synchronize the internal display timing generator to the input video source properly.
1 : normal operation

7.2.2 Color Space Conversion Control (Sub-Addresses 0x04−0x19)

Signed magnitude: MSB is sign bit, remaining bits are binary representation of magnitude. This is not a 2s complement notation.

Magnitude: Binary representation of magnitude.

csc_ric1(5:0): R/Cr input channel – G/Y output channel coefficient, integer part
{csc_r11 0x04(7:2)} [00 0000]
6-bit integer portion of coefficient that is multiplied with R/Cr input, to produce G/Y output (signed magnitude format)
csc_rfc1(9:0): R/Cr input channel – G/Y output channel, fractional part
{csc_r11 0x04(1:0) and
csc_r12 0x05(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce G/Y output (magnitude format)
csc_ric2(5:0): R/Cr input channel – B/Cb output channel, integer part
{csc_r21 0x06(7:2)} {csc_r21 0x06(7:2)}
6-bit integer portion of coefficient that is multiplied with R/Cr input, to produce B/Cb output (signed magnitude format)
csc_rfc2(9:0): R/Cr input channel – B/Cb output channel, fractional part
{csc_r21 0x06(1:0) and
csc_r22 0x07(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce B/Cb output (magnitude format)
csc_ric3(5:0): R/Cr input channel – R/Cr output channel, integer part
{csc_r31 0x08(7:2)} [000000]
6-bit integer portion of coefficient that is multiplied with R/Cr input, to produce R/Cr output (signed magnitude format)
csc_rfc3(9:0): R/Cr input channel − R/Cr output channel, fractional part
{csc_r31 0x08(1:0) and
csc_r32 0x09(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce R/Cr output (magnitude format)
csc_gic1(5:0): G/Y input channel – G/Y output channel, integer part
{csc_g11 0x0A(7:2)} [00 0000]
6-bit fractional portion of coefficient that is multiplied with R/Cr input, to produce R/Cr output (magnitude format)
csc_gfc1(9:0): G/Y input channel – G/Y output channel, fractional part
{csc_g11 0x0A(1:0) and
csc_g12 0x0B(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with G/Y input, to produce G/Y output (magnitude format)
csc_gic2(5:0): G/Y input channel – B/Cb output channel, integer part
{csc_g21 0x0C(7:2)} [00 0000]
6-bit integer portion of coefficient that is multiplied with G/Y input, to produce G/Y output (magnitude format)
csc_gfc2(9:0): G/Y input channel – B/Cb output channel, fractional part
{csc_g21 0x0C(1:0) and
csc_g22 0x0D(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with G/Y input, to produce B/Cb output (magnitude format)
csc_gic3(5:0): G/Y input channel – R/Cr output channel, integer part
{csc_g31 0x0E(7:2)} {csc_g31 0x0E(7:2)}
6-bit integer portion of coefficient that is multiplied with G/Y input, to produce R/Cr output (signed magnitude format)
csc_gfc3(9:0) G/Y input channel – R/Cr output channel, fractional part
{csc_g31 0x0E(1:0) and
csc_g32 0x0F(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with G/Y input, to produce R/Cr output (magnitude format)
csc_bic1(5:0): B/Cb input channel – G/Y output channel, integer part
{csc_b11 0x10(7:2)} [00 0000]
6-bit integer portion of coefficient that is multiplied with B/Cb input, to produce G/Y output (signed magnitude format)
csc_bfc1(9:0): B/Cb input channel – G/Y output channel, fractional part
{csc_b11 0x10(1:0) and
csc_b12 0x11(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with B/Cb input, to produce G/Y output (magnitude format)
csc_bic2(5:0): B/Cb input channel – B/Cb output channel, integer part
{csc_b21 0x12(7:2)} [00 0000]
6-bit integer portion of coefficient that is multiplied with B/Cb input, to produce B/Cb output (signed magnitude format)
csc_bfc2(9:0): B/Cb input channel – B/Cb output channel, fractional part
{csc_b21 0x12(1:0) and
csc_b22 0x13(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with B/Cb input, to produce B/Cb output (magnitude format)
csc_bic3(5:0): B/Cb input channel – R/Cr output channel, integer part
{csc_b31 0x14(7:2)} [00 0000]
6-bit integer portion of coefficient that is multiplied with B/Cb input, to produce R/Cr output (signed magnitude format)
csc_bfc3(9:0): B/Cb input channel – R/Cr output channel, fractional part
{csc_b31 0x14(1:0) and
csc_b32 0x15(7:0)}		 [00 0000 0000]
10-bit fractional portion of coefficient that is multiplied with B/Cb input, to produce R/Cr output (magnitude format)
csc_offset1(9:0): DAC channel 1 offset
{csc_offs1 0x16(7:0) and
csc_offs12 0x17(7:6)}		 [00 0000 0000]
Offset value for G/Y output (signed magnitude format)
csc_offset2(9:0): DAC channel 2 offset
{csc_offs12 0x17(5:0) and
csc_offs23 0x18(7:4)}		 [00 0000 0000]
Offset value for B/Cb output (signed magnitude format)
csc_offset3(9:0): DAC channel 3 offset
{csc_offs23 0x18(3:0) and
csc_offs3 0x19(7:2)}		 [00 0000 0000]
Offset value for R/Cr output (signed magnitude format)
csc_bypass: Bypass for CSC block
{csc_offs3 0x19(1)} [1]
0 : Color space conversion (CSC) not bypassed
1 : CSC bypassed
csc_uof_cntl: Under-/overflow control for CSC block
{csc_offs3 0x19(1)} [0]
Controls over-/underflow protection logic on color space converter
0 : Under-/overflow protection off
1 : Under-/overflow protection on

7.2.3 Test Control (Sub-Addresses 0x1A−0x1B)

tst_digbypass: Bypass to DAC inputs
{tst_cntl1 0x1A(7)} [0]
0 : Normal operation; nonbypass
1 : Digital logic bypassed to directly control DACs from input bus
tst_offset: Bypass for DAC offsets
{tst_cntl1 0x1A(6)} [0]
0 : Normal operation; logic not bypassed
1 : Programmed offsets are always added to DAC codes regardless of mode or dtg_state
tst_ydelay(1:0): Y delay path control
{tst_cntl2 0x1B(7:6)} [00]
Adjusts the delay of the Y channel during YCbCr modes
tst_fastramp: DAC test control, fast ramp
{tst_cntl2 0x1B(1)} [0]
0 : Normal operation
1 : DAC outputs a ramp at 2x clock rate.
tst_slowramp: DAC test control, slow ramp
{tst_cntl2 0x1B(0)} [0]
0 : Normal operation
1 : DAC outputs a ramp at 2x clock rate divided by 64,000. This mode has a higher priority than the one set by tst_fastramp

7.2.4 Data Path Control (Sub-Address 0x1C)

data_clk656_on: ITU-R.BT656 output clock control
{data_cntl 0x1C(7)} [0]
0 : D1CLKO output off
1 : D1CLKO output on
data_fsadj: Full-scale adjust control
{data_cntl 0x1C(6)} [0]
Selects which full-scale setting to use. See FSADJ<n> terminal description for nominal full-scale adjust resistor values.
0 : Use full-scale setting from resistor connected to FSADJ2 terminal
1 : Use full-scale setting from resistor connected to FSADJ1 terminal
data_ifir12_bypass: Bypass control 4:2:2 to 4:4:4
{data_cntl 0x1C(5)} [0]
0 : Interpolation filters before the CSC are in the data path, enabling 4:2:2 to 4:4:4 conversion internally. This mode should be used when the input data is in 4:2:2 format
1 : Interpolation filters before the CSC are bypassed. This mode should be used when the input data is in 4:4:4 format.
data_ifir35_bypass: Bypass control 2x interpolation
{data_cntl 0x1C(4)} [0]
0 : interpolation filters after the CSC are in the data path; enabling 1x to 2x interpolation of the video data.
1 : interpolation filters after the CSC are bypassed. This mode should be used when 1x DAC operation is desired.
data_tristate656: ITU-R.BT656 output bus
{data_cntl 0x1C(3)} [0]
0 : the ITU-R.BT656 output bus is active.
1 : the ITU-R.BT656 output bus is in the high-impedance state.
data_dman_cntl(2:0): Data manager control
{data_cntl 0x1C(2:0)} [011]
Selects the format for the input data manager, as follows:
dman_cntl MODE
000 30-bit YCbCr/RGB 4:4:4
001 16-bit RGB 4:4:4
010 15-bit RGB 4:4:4
011 20-bit YCbCr 4:2:2
100 10-bit YCbCr 4:2:2 (ITU mode)
Others (Reserved)

7.2.5 Display Timing Generator Control, Part 1 (Sub-Addresses 0x1D−0x3C)

dtg1_y_blank(9:0): Y channel blanking level amplitude control
{dtg1_y_sync_msb 0x23(5:4) and
dtg1_y_sync1_lsb 0x1D(7:0)}		 [10 0000 0000]
Sets the amplitude of the blanking level for the Y channel
dtg1_y_sync_low(9:0): Y channel low sync level amplitude control
{dtg1_y_sync_msb 0x23(3:2) and
dtg1_y_sync2_lsb 0x1E(7:0)}		 [00 0000 0000]
Sets the amplitude of the negative sync and equalization/serration/broad pulses for the Y channel
dtg1_y_sync_high(9:0): Y channel high sync level amplitude control
{dtg1_y_sync_msb 0x23(1:0) and
dtg1_y_sync3_lsb 0x1F(7:0)}		 [11 0000 0000]
Sets the amplitude of the positive sync for the Y channel
dtg1_cbcr_blank(9:0): Cb/Cr channel blanking level amplitude control
{dtg1_cbcr_sync_msb 0x24(5:4) and
dtg1_cbcr_sync1_lsb 0x20(7:0)}		 [10 0000 0000]
Sets the amplitude of the blanking level for the Cb and Cr channels
dtg1_cbcr_sync_low (9:0): Cb/Cr channel low sync level amplitude control
{dtg1_cbcr_sync_msb 0x24(3:2) and
dtg1_cbcr_sync2_lsb 0x21(7:0)}		 [00 0000 0000]
Sets the amplitude of the negative sync and equalization/serration/broad pulses for the Cb and Cr channels
dtg1_cbcr_sync_high(9:0): Cb/Cr channel high sync level amplitude control
{dtg1_cbcr_sync_msb 0x24(1:0) and
dtg1_cbcr_sync3_lsb 0x22(7:0)}		 [11 0000 0000]
Sets the amplitude of the positive sync for the Cb and Cr channels
dtg1_spec_a(7:0): Negative HSync width
{dtg1_spec_a 0x25(7:0)} [0010 1100] = [44d]
Width of negative excursion of tri-level (HDTV mode) or bi-level (SDTV mode) sync
dtg1_spec_b(7:0): End of active video to 0H
{dtg1_spec_b 0x26(7:0)} [0101 1000] = [88d]
Distance from end of active video to start of negative sync (SDTV mode) or to negative-to-positive transition of tri-level sync (HDTV mode)
dtg1_spec_c(7:0): Positive Hsync width (HDTV)/Equalization pulse (SDTV) width
{dtg1_spec_c 0x27(7:0)} [0010 1100] = [44d]
Width of positive excursion of tri-level (HDTV mode). Width of equalization pulses (SDTV mode)
dtg1_spec_d(8:0): Sync to active video(SDTV)/sync to broad pulse(HDTV)
{dtg1_spec_deh_msb 0x2B(7) and
dtg1_spec_d_lsb 0x28(7:0)}		 [0 1000 0100] = [132d]
Distance from leading edge of Hsync to start of active video (SDTV mode) or from negative-to-positive transition of tri-level sync to start of broad pulse (HDTV mode)
dtg1_spec_d1(7:0): Center equalization pulse to active video (SDTV)
{dtg1_spec_d1 0x29(7:0)} [0000 0000]
Distance from equalization pulse at center of line to active video (SDTV mode)
dtg1_spec_e(8:0): Sync to active video (HDTV)/Color bar start (VESA)
{dtg1_spec_deh_msb 0x2B(6) and
dtg1_spec_e_lsb 0x2A(7:0)}		 [0 1100 0000] = [192d]
Distance from negative-to-positive transition of tri-level sync to start of active video (HDTV mode). In case color bars are activated in VESA mode, this parameter specifies the start of the color bar with respect to the horizontal sync
dtg1_spec_h(9:0): Broad pulse duration (SDTV)
{dtg1_spec_deh_msb 0x2B(1:0) and
dtg1_spec_h_lsb 0x2C(7:0)}		 [00 0000 0000]
Duration of broad pulse (SDTV mode)
dtg1_spec_i(11:0): Full-line broad pulse duration (SDTV)
{dtg1_spec_i_msb 0x2D(3:0) and
dtg1_spec_i_lsb 0x2E(7:0)}		 [0000 0000 0000]
Duration of full-line broad pulse (SDTV mode)
dtg1_spec_k(10:0): End of active video to sync (SDTV)/end of broad pulse to sync (HDTV)
{dtg1_spec_k_msb 0x30(2:0) and
dtg1_spec_k_lsb 0x2F(7:0)}		 [000 0101 1000] = [88d]
Distance from end of active video to leading edge of sync (SDTV) or from end of broad pulse to negative-to-positive transition of tri-level sync (HDTV)
dtg1_spec_k1(7:0): End of active video in first half of line to center equalization pulse (SDTV)
{dtg1_spec_k1 0x31(7:0)} [00000000]
Distance from end of active video in first half of line to center equalization pulse for SDTV line type ACTIVE_NEQ
dtg1_spec_g(11:0): 1/2 of line length (SDTV)
{dtg1_spec_g_msb 0x33(3:0) and
dtg1_spec_g_lsb 0x32(7:0)}		 [0000 0101 1000] = [88d]
Half the line length. Only used in the calculations of SDTV line types.
dtg1_total_pixels(12:0): Total pixels per line (SDTV/HDTV/VESA)
{dtg1_total_pixels_msb 0x34(4:0) and
dtg1_total_pixels_lsb 0x35(7:0)}		 [0 0101 0010 0000] = [1312d]
Total number of pixels per line. Used in all DTG modes.
dtg1_field_flip: FID/F polarity select
{dtg1_fieldflip_linecnt_msb 0x36(7)} [0]
0 : DTG is initialized to field1 at active VS edge when a 0 is received on FID signal or F bit
1 : DTG is initialized to field1 at active VS edge when a 1 is received on FID signal or F bit
dtg1_linecnt(10:0): DTG start line number
{dtg1_fieldflip_linecnt_msb 0x36(2:0) and
dtg1_linecnt_lsb 0x37(7:0)}		 [000 0000 0001]
Sets the starting line number for the DTG when Vsync input or V-bit is asserted (vertical display control)
dtg1_on: DTG on/off
{dtg1_mode 0x38(7)} [1]
0 : DTG output held to dtg_y_blank value
1 : DTG on
dtg1_pass_through: DTG pass-through
{dtg1_mode 0x38(4)} [0]
0 : Video data blocked during certain line types
1 : Video data passed during certain line types
See DTG Line Types Overview (Section 6.7.3) for details.
dtg1_mode(3:0): DTG mode selection
{dtg1_mode 0x38(3:0)} [0110]
Selects the operation mode of the DTG according to the following table. Each setting is either an SDTV, HDTV or VESA format, as shown:
dtg1_mode MODE
0000 ATSC mode 1080P (SMPTE 274M progressive) [HDTV]
0001 ATSC mode 1080I (SMPTE274M interlaced) [HDTV]
0010 ATSC mode 720P (SMPTE296M progressive) [HDTV]
0011 Generic mode for HDTV [HDTV]
0100 ATSC mode 480I (SDTV 525 lines interlaced) [SDTV]
0101 ATSC mode 480P (SDTV 525 lines progressive) [SDTV]
0110 VESA master [VESA]
0111 VESA slave [VESA]
1000 SDTV 625 interlaced [SDTV]
1001 Generic mode for SDTV [SDTV]
Others [Null]
dtg1_frame_size(10:0): Generic mode frame size
{dtg1_frame_field_size_msb 0x39(6:4) and
dtg1_framesize_lsb 0x3A(7:0)}		 [011 0000 0000]
Determines number of lines per frame when in generic mode
dtg1_field_size(10:0): Generic mode field size
{dtg1_frame_field_size_msb 0x39(2:0) and
dtg1_fieldsize_lsb 0x3B(7:0)}		 [000 0010 0000]
Determines number of lines in field 1 when in generic mode. This number should be programmed higher than frame_size for progressive scan formats.
dtg1_vesa_cbar_size(7:0): Color bar pattern, width
{dtg1_vesa_cbar_size 0x3C(7:0)} [1000 0000]
Sets the width of each color bar in the color bar test pattern. This test pattern is only available when the DTG is in VESA mode.

7.2.6 DAC Control (Sub-Addresses 0x3D−0x40)

dac_i2c_cntl: DAC I2C control
{dac_cntl_msb 0x3D(6)} [0]
0 : DAC normal operation
1 : DAC inputs are fixed to values of <dac_cntl> registers
dac1_cntl(9:0): DAC1 input value
{dac_cntl_msb 0x3D(5:4) and
dac1_cntl_lsb 0x3E(7:0)}		 [00 0000 0000]
Direct input to G/Y DAC
dac2_cntl(9:0): DAC2 input value
{dac_cntl_msb 0x3D(3:2) and
dac2_cntl_lsb 0x3F(7:0)}		 [00 0000 0000]
Direct input to B/Cb DAC
dac3_cntl(9:0): DAC3 input value
{dac_cntl_msb 0x3D(1:0) and
dac3_cntl_lsb 0x40(7:0)}		 [00 0000 0000]
Direct input to R/Cr DAC

7.2.7 Clip/Shift/Multiplier Control (Sub-Addresses 0x41−0x4F)

csm_clip_gy_low(7:0): G/Y low clipping value
{csm_clip_gy_low 0x41(7:0)} [0100 0000]
Sets the value at which low end clipping occurs on G/Y channel, if clipping is enabled. Range is 0−255.
csm_clip_bcb_low(7:0): B/Cb low clipping value
{csm_clip_bcb_low 0x42(7:0)} [0100 0000]
Sets the value at which low end clipping occurs on B/Cb channel, if clipping is enabled. Range is 0−255.
csm_clip_rcr_low(7:0): R/Cr low clipping value
{csm_clip_rcr_low 0x43(7:0)} [0100 0000]
Sets the value at which low end clipping occurs on R/Cr channel, if clipping is enabled. Range is 0−255.
csm_clip_gy_high(7:0): G/Y high clipping value
{csm_clip_gy_high 0x44(7:0)} [0101 0011]
Sets the value at which high end clipping occurs on G/Y channel, if clipping is enabled.
High clip value = 1023-csm_clip_gy_high
csm_clip_bcb_high(7:0): B/Cb high clipping value
{csm_clip_bcb_high 0x45(7:0)} [0011 1111]
Sets the value at which high end clipping occurs on B/Cb channel, if clipping is enabled.
High clip value = 1023−csm_clip_bcb_high
csm_clip_rcr_high(7:0): R/Cr high clipping value
{csm_clip_rcr_high 0x46(7:0)} [0011 1111]
Sets the value at which high end clipping occur on R/Cr channel, if clipping is enabled.
High clip value = 1023−csm_clip_rcr_highs
csm_shift_gy(7:0): G/Y shift value
{csm_shift_gy 0x47(7:0)} [0100 0000]
Value that G/Y data is shifted downwards. Range 0−255. Note: it is possible to shift the data so much that a roll over condition occurs.
csm_shift_bcb(7:0): B/Cb shift value
{csm_shift_bcb 0x48(7:0)} [0100 0000]
Value that B/Cb data is shifted downwards. Range: 0−255. Note: It is possible to shift the data so much that a roll over condition occurs.
csm_shift_rcr(7:0): R/Cr shift value
{csm_shift_rcr 0x49(7:0)} [0100 0000]
Value that B/Cb data is shifted downwards. Range: 0−255. Note: It is possible to shift the data so much that a roll over condition occurs.
csm_mult_gy_on: G/Y scaling on/off
{csm_gy_cntl_mult_msb 0x4A(7)} [0]
0 : Scaling for G/Y channel off
1 : Scaling for G/Y channel on
csm_shift_gy_on: G/Y shifting on/off
{csm_gy_cntl_mult_msb 0x4A(6)} [0]
0 : Shifting for G/Y channel off
1 : Shifting for G/Y channel on
csm_gy_high_clip_on: G/Y high-end clipping on/off
{csm_gy_cntl_mult_msb 0x4A(5)} [0]
0 : G/Y data clipping at high end off
1 : G/Y data clipping at high end on
csm_gy_low_clip_on: G/Y low-end clipping on/off
{csm_gy_cntl_mult_msb 0x4A(4)} [0]
0 : G/Y data clipping at low end off
1 : G/Y data clipping at low end on
csm_of_cntl: CSM overflow control
{csm_gy_cntl_mult_msb 0x4A(3)} [1]
Controls overflow protection of the CSM multiplier
0 : Overflow protection off
1 : Overflow protection on
Numerical format of the CSM mult registers:
The 11-bit value is a binary weighted value in the range 0−1.999.
Thus: csm_mult_<gy,rcr,bcb>(10:0) = [(multiplier in range 0..1.999)/1.999] × 2047.
csm_mult_gy(10:0): G/Y scaling value
{csm_gy_cntl_mult_msb 0x4A(2:0) and
csm_mult_gy_lsb 0x4C(7:0)}		 [000 0000 0000]
Multiplication factor for G/Y channel in CSM. Range: 0−1.999.
Note: it is possible to scale the input so much that a rollover occurs.
csm_mult_bcb(10:0): B/Cb scaling value
{csm_mult_bcb_rcr_msb 0x4B(6:4) and
csm_mult_bcb_lsb 0x4D(7:0)}		 [000 0000 0000]
Multiplication factor for B/Cb channel in CSM. Range: 0−1.999.
Note: it is possible to scale the input so much that a rollover occurs.
csm_mult_rcr(10:0): R/Cr scaling value
{csm_mult_bcb_rcr_msb 0x4B(2:0) and
csm_mult_rcr_lsb 0x4E(7:0)}		 [000 0000 0000]
Multiplication factor for R/Cr channel in CSM. Range: 0−1.999.
Note: it is possible to scale the input so much that a rollover occurs.
csm_mult_rcr_on: R/Cr scaling on/off
{csm_rcr_bcb_cntl 0x4F(7)} [0]
0 : Scaling for R/Cr channel off
1 : Scaling for R/Cr channel on
csm_mult_bcb_on: B/Cb scaling on/off
{csm_rcr_bcb_cntl 0x4F(6)} [0]
0 : Scaling for B/Cb channel of
1 : Scaling for B/Cb channel on
csm_shift_rcr_on: R/Cr shifting on/off
{csm_rcr_bcb_cntl 0x4F(5)} [0]
0 : Shifting for R/Cr channel off
1 : Shifting for R/Cr channel on
csm_shift_bcb_on: B/Cb shifting on/off
{csm_rcr_bcb_cntl 0x4F(4)} [0]
0 : Shifting for B/Cb channel off
1 : Shifting for B/Cb channel on
csm_rcr_high_clip_on: R/Cr high-end clipping on/off
{csm_rcr_bcb_cntl 0x4F(3)} [0]
0 : R/Cr data clipping at high end off
1 : R/Cr data clipping at high end on
csm_rcr_low_clip_on: R/Cr low-end clipping on/off
{csm_rcr_bcb_cntl 0x4F(2)} [0]
0 : R/Cr data clipping at low end off
1 : R/Cr data clipping at low end on
csm_bcb_high_clip_on: B/Cb high-end clipping on/off
{csm_rcr_bcb_cntl 0x4F(1)} [0]
0 : B/Cb data clipping at high end off
1 : B/Cb data clipping at high end on
csm_bcb_low_clip_on: B/Cb low-end clipping on/off
{csm_rcr_bcb_cntl 0x4F(0)} [0]
0 : B/Cb data clipping at low end off
1 : B/Cb data clipping at low end on

7.2.8 Display Timing Generator Control, Part 2 (Sub-Addresses 0x50−0x82)

dtg2_bp<n>(10:0): breakpoint<n> line number
{see register map table} [000 0000 0000]
DTG outputs line type dtg2_linetype<n> until line number of dtg2_bp<n+1> is reached. (n = 1..16)
dtg2_linetype<n>(3:0): Line type for dtg2_bp<n>
{see register map table} [0000]
The DTG outputs a line format corresponding to the table below until the next breakpoint line number is reached. (n = 1..16)
LINE TYPE MODE
0000 ACTIVE_VIDEO
0001 FULL_NTSP
0010 FULL_BTSP
0011 NTSP_NTSP
0100 BTSP_BTSP
0101 NTSP_BTSP
0110 BTSP_NTSP
0111 ACTIVE_NEQ
1000 NSP_ACTIVE
1001 FULL_NSP
1010 FULL_BSP
1011 FULL_NEQ
1100 NEQ_NEQ
1101 BSP_BSP
1110 BSP_NEQ
1111 NEQ_BSP
dtg2_hlength(9:0): HS_OUT duration
{dtg2_hlength_msb_hdly_msb 0x71(7:6) and dtg2_hlength_lsb 0x70(7:0)} [00 0110 0000]
Sets the duration of the HS_OUT output signal
dtg2_hdly(12:0): HS_OUT delay
{dtg2_hlength_msb_hdly_msb 0x71(4:0) and dtg2_hdly_lsb 0x72(7:0)} [0 0000 0000 0010]
Sets the pixel value that the HS_OUT signal is asserted on.
Note: when programmed to a value higher than the total number of pixels per line, there will be no HS_OUT output.
dtg2_vlength1(9:0): VS_OUT duration, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(7:6) and dtg2_vlength1_lsb 0x73(7:0)} [00 0000 0011]
Sets the duration of the VS_OUT output signal during progressive scan video modes or during the vertical blank interval of field 1 in interlaced video modes.
dtg2_vdly1(10:0): VS_OUT delay, field 1
{dtg2_vlength1_msb_vdly1_msb 0x74(2:0) and dtg2_vdly1_lsb 0x75(7:0)} [000 0000 0011]
Sets the line number that the VS_OUT signal is asserted on for progressive video modes or for field 1 of interlaced video modes.
Note: when programmed to a value higher than the total number of lines per frame, there is no VS_OUT output.
dtg2_vlength2(9:0): VS_OUT duration, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(7:6) and dtg2_vlength2_lsb 0x76(7:0)} [00 0000 0000]
Sets the duration of the VS_OUT output signal during the vertical blank interval of field 2 in interlaced video modes. In progressive video modes, this register must be set to all 0.
dtg2_vdly2(10:0): VS_OUT delay, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(2:0) and dtg2_vdly2_lsb 0x78(7:0)} [111 1111 1111]
Sets the line number that the VS_OUT signal is asserted on for field 2 of interlaced scan video modes. For progressive scan video modes, this register must be set to all 1.
dtg2_hs_in_dly(12:0): DTG horizontal delay
{dtg2_hs_in_dly_msb 0x79(4:0) and dtg2_hs_in_dly_lsb 0x7A(7:0)} [0 0000 0011 1101]
Sets the number of pixels that the DTG startup is horizontally delayed with respect to HS input for dedicated timing modes or EAV input for embedded timing modes.
Note: It is possible to delay startup past the end of a line when this delay is programmed higher than the total number of pixels per line.
dtg2_vs_in_dly(10:0): DTG vertical delay
{dtg2_vs_in_dly_msb 0x7B(2:0) and dtg2_vs_in_dly_lsb 0x7C(7:0)} [000 0000 0011]
Sets the number of lines that the DTG startup is vertically delayed with respect to VS input for dedicated timing modes or the line counter value for embedded timing.
Note: It is possible to delay startup past the end of a frame when this delay is programmed higher than the total number of lines per frame.
dtg2_pixel_cnt(15:0): Pixel count readback
{dtg2_pixel_cnt_msb 0x7D(7:0) and dtg2_pixel_cnt_lsb 0x7E(7:0)}
Reports the number of clock 1x rising edges between consecutive Hsync input pulses
dtg2_ip_fmt: Interlaced/progressive-scan indicator
{dtg2_line_cnt_msb 0x7F(7)}
Indicates whether current video frame is progressive (0) or interlaced (1)
dtg2_line_cnt(10:0): Line count readback
{dtg2_lined_cnt_msb 0x7F(2:0) and dtg2_line_cnt_lsb 0x80(7:0)}
Reports the number of Hsync input pulses between consecutive dtg_start signals (that is, over one frame period)
dtg2_fid_de_cntl: FID (field-ID)/DE (data enable)input selection for FID terminal
{dtg2_cntl 0x82(7)} [0]
Controls interpretation of signal on FID terminal
0 : Signal interpeted as FieldID
1 : If the DTG is programmed to the VESA mode, the FID pin becomes a data-enable input pin. Data enable is assumed high during the active video window, and low outside this area. This is compatible with the DE signal from TI DVI receivers. Data is passed through the THS8200 only when data enable is high. Otherwise, the input data is overridden by the THS8200 internally programmed blanking value. If the DTG is programmed in the SDTV or HDTV video mode with dedicated timing signals, a 1 in this register location causes the THS8200 to generate an internal FieldID value from the relative alignment of Hsync and Vsync inputs, rather than using the signal on the FID input pin (which is ignored). This is for EIA-861 compliant operation for video-over-DVI 1.0 (with HDCP) where there is no dedicated FID signal available but the even/odd field ID is determined from Hsync/Vsync alignment.
dtg2_rgb_mode_on: RGB/YPbPr mode selection
{dtg2_cntl 0x82(6)} [1]
This selection affects the relative blank vs video level position: on R,G,B, and Y channels an offset is added to the DAC outputs
0 : YPbPr mode (blanking at bottom range for Y – mid-range for Pb, Pr channels)
1 : RGB mode (blanking at bottom ranges for all channels)
dtg2_embedded_timing: Video sync input source
{dtg2_cntl 0x82(5)} [0]
0 : Timing of video input bus is derived from HS, VS, and FID dedicated inputs
1 : Timing of video input bus is assumed embedded in video data using SAV/EAV code sequences.
dtg2_vsout_pol: VS_OUT polarity
{dtg2_cntl 0x82(4)} [1]
0 : Negative polarity
1 : Positive polarity
dtg2_hsout_pol: HS_OUT polarity
{dtg2_cntl 0x82(3)} [1]
0 : Negative polarity
1 : Positive polarity
dtg2_fid_pol: FID polarity
{dtg2_cntl 0x82(2)} [1]
0 : Negative polarity
1 : Positive polarity

dtg2_vs_pol: VS_IN polarity
{dtg2_cntl 0x82(1)} [1]
0 : Negative polarity
1 : Positive polarity
dtg2_hs_pol: HS_IN polarity
{dtg2_cntl 0x82(0)} [1]
0 : Negative polarity
1 : Positive polarity
misc_ppl(15:0): HS high
{misc_ppl_msb 0x87(7:0) and misc_ppl_lsb 0x86(7:0)}
Reports the number of clock cycles HS was held high
misc_lpf(15:0): VS high
{misc_lpf_msb 0x89(7:0) and misc_lpf_lsb 0x88(7:0)}
Reports the number of HS counts that VS was held high.

7.2.9 CGMS Control (Sub-Addresses 0x83−0x85)

cgms_en: CGMS enable
{cgms_cntl_header 0x83(6)} [0]
0 : No CGMS data inserted
1 : CGMS data inserted on line 41 in SDTV mode
cgms_header: CGMS header
{cgms_cntl_header 0x83(5:0)} [00 0000]
cgms_payload(13:0): CGMS payload
{cgms_payload_msb 0x84(5:0) and
cgms_payload_lsb 0x85(7:0)}		 [00 0000 0000 0000]
CGMS payload data

7.3 THS8200 Preset Mode Line Type Definitions

The following are the (line type, breakpoint) combinations that are preprogrammed when selecting the corresponding DTG preset setting.

7.3.1 SMPTE_274P (1080P)

Breakpoints Line Type
6 FULL_BTSP
42 FULL_NTSP
1122 ACTIVE_VIDEO
1126 FULL_NTSP
frame_size = 10001100101; 1125d
field_size = 11111111111; not needed

7.3.2 274M Interlaced (1080I)

Breakpoints Line Type
6 BTSP_BTSP
7 NTSP_NTSP
21 FULL_NTSP
561 ACTIVE_VIDEO
563 FULL_NTSP
564 NTSP_BTSP
568 BTSP_BTSP
569 BTSP_NTSP
584 FULL_NTSP
1124 ACTIVE_VIDEO
1126 FULL_NTSP
frame_size = 10001100101; 1125d
field_size = 01000110011; 563d

7.3.3 296M Progressive (720P)

Breakpoints Line Type
6 FULL_BTSP
26 FULL_NTSP
746 ACTIVE_VIDEO
751 FULL_NTSP
frame_size = 01011101110; 750d
field_size = 11111111111; not needed

7.3.4 SDTV 525 Interlaced Mode

Breakpoints Line Type
4 NEQ_NEQ
7 BSP_BSP
10 NEQ_NEQ
20 FULL_NSP
263 ACTIVE_VIDEO
264 ACTIVE_NEQ
266 NEQ_NEQ
267 NEQ_BSP
269 BSP_BSP
270 BSP_NEQ
272 NEQ_NEQ
273 FULL_NEQ
282 FULL_NSP
283 NSP_ACTIVE
526 ACTIVE_VIDEO
frame_size = 1000001101; 525d
field_size = 00100000111; 263d

7.3.5 SDTV 525 Progressive Mode

Breakpoints Line Type
10 FULL_NSP
16 FULL_BSP
46 FULL_NSP
526 ACTIVE_VIDEO
frame_size = 01000001101; 525d
field_size = 11111111111; not needed

7.3.6 SDTV 625 Interlaced Mode

Breakpoints Line Type
3 BSP_BSP
4 BSP_NEQ
6 NEQ_NEQ
23 FULL_NSP
24 NSP_ACTIVE
311 ACTIVE_VIDEO
313 NEQ_NEQ
314 NEQ_BSP
316 BSP_BSP
318 NEQ_NEQ
319 FULL_NEQ
336 FULL_NSP
623 ACTIVE_VIDEO
624 ACTIVE_NEQ
626 NEQ_NEQ
frame_size = 01001110001; 625d
field_size = 00100111000; 312d