JAJSLX6 September   2023 THVD1330

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 機能ブロック図
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 Device Support
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 サポート・リソース
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Switching Characteristics

Over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver: 32Mbps
tr, tf Differential output rise/fall time RL = 54Ω, CL = 50 pF, PRR=500KHz, Across full range of process, voltage and temperature See Figure 6-3 3 4.5 10 ns
tPHL, tPLH Propagation delay 5 8.5 16 ns
tSK(P) Pulse skew, |tPHL – tPLH| 1.5 ns
tSK(PP) Part to part skew 6 ns
tPHL, tPLH Propagation delay RL = 54Ω , CL = 50pF, VCC = 3.3 V +/ 3%, TA = -20°C to 85°C 6 13.8 ns
tPHZ Disable time PRR = 500KHz, RL = 110 Ω, CL = 50 pF See Figure 6-4 and Figure 6-5 25 ns
tPLZ Disable time PRR = 500KHz, RL = 110 Ω, CL = 50 pF 26 ns
tPZH Enable time RE = 0 V, PRR = 500KHz, RL = 110 Ω, CL = 50 pF 31 ns
tPZL 26 ns
tPZH2 Enable time RE = VCC, PRR = 100KHz, RL = 110 Ω± 1%, CL = 50 pF ± 20%, 50% to 2.3V 6 µs
tPZL2 6 µs
Receiver: 32Mbps
tr, tf Differential output rise/fall time PRR = 500KHz, CL = 15pF, Across process, full range of voltage and ambient temperature See Figure 6-6 1 2 5 ns
tPHL, tPLH Propagation delay 12.5 20 25 ns
tSK(P) Pulse skew, |tPHL – tPLH| 1.5 ns
tSK(PP) Part to part skew 8 ns
tPHL, tPLH Propagation delay PRR = 500KHz, CL = 15pF, VCC = 3.3V +/- 3%, TA = -20°C to 85°C 13 20 ns
tPHL, tPLH Propagation delay PRR = 500KHz, CL = 30pF, VCC = 3.3V +/- 3%, TA = -20°C to 85°C 13.4 21 ns
tPHZ Output disable time from high-level PRR = 500KHz, CL= 15 pF  See Figure 6-7 and Figure 6-8 20 ns
tPLZ Output disable time from low-level PRR = 500KHz, CL= 15 pF  15 ns
tPZH Output enable time to high-level DE = VCC , PRR = 500KHz, CL = 15pF  15 ns
tPZL Output enable time to low-level 15 ns
tPZH2 Output enable time to high-level DE = 0V , PRR = 100KHz, 50% to 1.5V, CL = 15pF ± 20% 6 µs
tPZL2 Output enable time to low-level 6 µs