JAJSFG1E May   2018  – May 2019 THVD1410 , THVD1450 , THVD1451 , THVD1452

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      THVD1410およびTHVD1450の概略回路図
      2.      THVD1451の概略回路図
      3.      THVD1452の概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
    3.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  ESD Ratings [IEC]
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Power Dissipation
    7. 7.7  Electrical Characteristics
    8. 7.8  Switching Characteristics
    9. 7.9  Typical Characteristics: All Devices
    10. 7.10 Typical Characteristics: THD1450, THVD1451 and THVD1452
    11. 7.11 Typical Characteristics: THVD1410
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Functional Modes for THVD1410 and THVD1450
      2. 9.4.2 Device Functional Modes for THVD1451
      3. 9.4.3 Device Functional Modes for THVD1452
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
    2. 13.2 デベロッパー・ネットワークの製品に関する免責事項
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DRB|8
サーマルパッド・メカニカル・データ
発注情報

9.4.1 Device Functional Modes for THVD1410 and THVD1450

When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is negative.

When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output A turns high and B turns low.

Table 1. Driver Function Table for THVD1410 and THVD1450

INPUT ENABLE OUTPUTS FUNCTION
D DE A B
H H H L Actively drive bus high
L H L H Actively drive bus low
X L Z Z Driver disabled
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus high by default

When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high. When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+ and VTH- the output is indeterminate.

When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Table 2. Receiver Function Table for THVD1410 and THVD1450

DIFFERENTIAL INPUT ENABLE OUTPUT FUNCTION
VID = VA – VB RE R
VTH+ < VID L H Receive valid bus high
VTH- < VID < VTH+ L ? Indeterminate bus state
VID < VTH- L L Receive valid bus low
X H Z Receiver disabled
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output