JAJSFG1E May   2018  – May 2019 THVD1410 , THVD1450 , THVD1451 , THVD1452

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      THVD1410およびTHVD1450の概略回路図
      2.      THVD1451の概略回路図
      3.      THVD1452の概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
    3.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  ESD Ratings [IEC]
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Power Dissipation
    7. 7.7  Electrical Characteristics
    8. 7.8  Switching Characteristics
    9. 7.9  Typical Characteristics: All Devices
    10. 7.10 Typical Characteristics: THD1450, THVD1451 and THVD1452
    11. 7.11 Typical Characteristics: THVD1410
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Functional Modes for THVD1410 and THVD1450
      2. 9.4.2 Device Functional Modes for THVD1451
      3. 9.4.3 Device Functional Modes for THVD1452
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
        5. 10.2.1.5 Transient Protection
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
    2. 13.2 デベロッパー・ネットワークの製品に関する免責事項
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DRB|8
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

THVD1410, THVD1450 Devices
8-Pin D Package (SOIC)
Top View
THVD1410, THVD1450 Devices
8-Pin DGK Package (VSSOP)
Top View
THVD1450 Device
8-Pin DRB Package (VSON)
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME D DGK DRB
A 6 6 6 Bus input/output Bus I/O port, A (complementary to B)
B 7 7 7 Bus input/output Bus I/O port, B (complementary to A)
D 4 4 4 Digital input Driver data input
DE 3 3 3 Digital input Driver enable, active high (2-MΩ internal pull-down)
GND 5 5 5 Ground Device ground
R 1 1 1 Digital output Receive data output
VCC 8 8 8 Power 3.3-V to 5-V supply
RE 2 2 2 Digital input Receiver enable, active low (2-MΩ internal pull-up)
Thermal Pad — — I/O No electrical connection. Should be connected to GND for optimal thermal performance.
THVD1451 Device
8-Pin D Package (SOIC)
Top View
THVD1451 Device
8-Pin DRB Package (VSON)
Top View

Pin Functions

PIN I/O Description
NAME D DRB
A 8 8 Bus input Bus input, A (complementary to B)
B 7 7 Bus input Bus input, B (complementary to A)
D 3 3 Digital input Driver data input
GND 4 4 Ground Device ground
R 2 2 Digital output Receive data output
VCC 1 1 Power 3.3-V to 5-V supply
Y 5 5 Bus output Digital bus output, Y (Complementary to Z)
Z 6 6 Bus output Digital bus output, Z (Complementary to Y)
Thermal Pad — I/O No electrical connection. Should be connected to GND for optimal thermal performance.
THVD1452 Device
14-Pin D Package (SOIC)
Top View
NC – No internal connection
THVD1452 Device
10-Pin DGS Package (VSSOP)
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME D DGS
A 12 9 Bus input Bus input, A (complementary to B)
B 11 8 Bus input Bus input, B (complementary to A)
D 5 4 Digital input Driver data input
DE 4 3 Digital input Driver enable, active high (2-MΩ internal pull-down)
GND 6, 7(1) 5 Ground Device ground
NC 1, 8 — — Internally not connected
R 2 1 Digital output Receive data output
VCC 13, 14(1) 10 Power 3.3-V to 5-V supply
Y 9 6 Bus output Digital bus output, Y (Complementary to Z)
Z 10 7 Bus output Digital bus output, Z (Complementary to Y)
RE 3 2 Digital input Receiver enable, active low (2-MΩ internal pull-up)
(1) These pins are internally connected