JAJSO69A january   2023  – july 2023 THVD1454

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings [IEC]
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics_500 kbps
    9. 6.9  Switching Characteristics_20 Mbps
    10. 6.10 Switching Characteristics_Termination resistor
    11. 6.11 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 On-Chip Switchable Termination
      2. 8.4.2 Operational Data rate
      3. 8.4.3 Protection Features
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 サード・パーティ製品に関する免責事項
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Switching Characteristics_500 kbps

500-kbps (with SLR = VCC) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V, unless otherwise noted. (1) 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
tr, tf Differential output rise/fall time RL = 54 Ω, CL = 50 pF
See Figure 7-3
 VCC = 3 to 3.6 V, Typical at 3.3V 200 250 600 ns
VCC = 4.5 to 5.5 V, Typical at 5 V 220 270 600 ns
tPHL, tPLH Propagation delay VCC = 3 to 3.6 V, Typical at 3.3V 260 500 ns
VCC = 4.5 to 5.5 V, Typical at 5 V 260 450 ns
tSK(P) Pulse skew, |tPHL – tPLH| VCC = 3 to 3.6 V, Typical at 3.3V 2 15 ns
VCC = 4.5 to 5.5 V, Typical at 5 V 2 15 ns
tPHZ, tPLZ Disable time RE = X See Figure 7-4 and Figure 7-5
 80 200 ns
tPZH, tPZL Enable time RE = 0 V 200 650 ns
RE = VCC 6 11 µs
Receiver
tr, tf Output rise/fall time CL = 15 pF See Figure 7-6  5 20 ns
tPHL, tPLH Propagation delay 620 1200 ns
tSK(P) Pulse skew, |tPHL – tPLH| 10 40 ns
tPHZ, tPLZ Disable time DE = X See Figure 7-7  20 60 ns
tPZH(1) Enable time DE = VCC 80 155 ns
tPZL(1) Enable time DE = VCC 650 1250 ns
tPZH(2),
tPZL(2)		 Enable time DE = 0 V See Figure 7-8  7 12 μs
(1)  A, B are RX input, Y/Z are driver output terminals in Full duplex mode