JAJSDK5A July   2017  – November 2018 THVD1500

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Dissipation
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
    2. 12.2 デベロッパー・ネットワークの製品に関する免責事項
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
|VOD| Driver differential output voltage magnitude RL = 60 Ω, -7 V ≤ Vtest ≤ 12 (See Figure 8) 1.5 2 V
RL = 100 Ω (See Figure 9) 2 2.5 V
RL = 54 Ω (See Figure 9) 1.5 2 V
Δ|VOD| Change in differential output voltage RL = 54 Ω or 100 Ω (See Figure 9) –50 50 mV
VOC Common-mode output voltage RL = 54 Ω or 100 Ω (See Figure 9) 1 VCC/2 3 V
ΔVOC(SS) Steady-state common-mode output voltage RL = 54 Ω or 100 Ω (See Figure 9) –50 50 mV
VOC(PP) Peak-to-peak common-mode output voltage RL = 54 Ω or 100 Ω (See Figure 9) 450 mV
IOS Short-circuit output current DE = VCC, -7 V ≤ VO ≤ 12 V, or A pin shorted to B pin –100 100 mA
Receiver
II1 Bus input current DE = 0 V,
VCC = 0 V or 5.5 V 		VI = 12 V 75 100 µA
VI = -7 V -97 -70 µA
RA, RB Bus input impedance VA = -7 V, VB = 12 V and
VA = 12 V, VB = -7 V (See Figure 14)		 96 kΩ
VTH+ Positive-going input threshold voltage See(1) –70 –50 mV
VTH- Negative-going input threshold voltage –200 –150 See(1) mV
VHYS Input hysteresis 20 50 mV
VOH Output high voltage IOH = -8 mA 4 VCC - 0.3 V
VOL Output low voltage IOL = 8 mA 0.2 0.4 V
IOZ Output high-impedance current VO = 0 V or VCC, RE = VCC -1 1 µA
IOSR Output short-circuit current RE = 0, DE = 0, See Figure 13 95 mA
Logic
IIN Input current
(D, DE, RE)		 4.5 V ≤ VCC ≤ 5.5 V –5 0 5 µA
Supply
ICC Supply current (quiescent) Driver and receiver enabled RE = 0 V, DE = VCC, No load 440 660 µA
Driver enabled, receiver disabled RE = VCC, DE = VCC, No load 295 420 µA
Driver disabled, receiver enabled RE = 0 V, DE = 0 V, No load 275 400 µA
Driver and receiver disabled RE = VCC, DE = 0 V, D = open, No load 0.1 1 µA
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.