JAJSHN2B
July 2019 – October 2021
THVD2410
,
THVD2450
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
ESD Ratings [IEC]
6.4
Recommended Operating Conditions
6.5
Thermal Information
6.6
Power Dissipation
6.7
Electrical Characteristics
6.8
Switching Characteristics: THVD2410
6.9
Switching Characteristics: THVD2450
6.10
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagrams
8.3
Feature Description
8.3.1
±70-V Fault Protection
8.3.2
Integrated IEC ESD and EFT Protection
8.3.3
Driver Overvoltage and Overcurrent Protection
8.3.4
Enhanced Receiver Noise Immunity
8.3.5
Receiver Fail-Safe Operation
8.3.6
Low-Power Shutdown Mode
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.1.1
Data Rate and Bus Length
9.2.1.2
Stub Length
9.2.1.3
Bus Loading
9.2.1.4
Transient Protection
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Device Support
12.1.1
Third-Party Products Disclaimer
12.2
Receiving Notification of Documentation Updates
12.3
サポート・リソース
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
D|8
MSOI002K
DRB|8
MPDS118K
DGK|8
MPDS028E
サーマルパッド・メカニカル・データ
DRB|8
QFND043N
発注情報
jajshn2b_oa
jajshn2b_pm
11
Layout