JAJSOM2 April   2024 THVD4421

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics_RS-485_500kbps
    9. 5.9  Switching Characteristics_RS-485_20Mbps
    10. 5.10 Switching Characteristics, Driver_RS232
    11. 5.11 Switching Characteristics, Receiver_RS232
    12. 5.12 Switching Characteristics_MODE switching
    13. 5.13 Switching Characteristics_RS-485_Termination resistor
    14. 5.14 Switching Characteristics_Loopback mode
    15. 5.15 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Integrated IEC ESD and EFT Protection
      2. 7.3.2 Protection Features
      3. 7.3.3 Receiver Fail-Safe Operation
      4. 7.3.4 Low-Power Shutdown Mode
      5. 7.3.5 On-chip Switchable Termination Resistor
      6. 7.3.6 Operational Data Rate
      7. 7.3.7 Diagnostic Loopback
      8. 7.3.8 Integrated Charge Pump for RS-232
    4. 7.4 Device Functional Modes
      1. 7.4.1 RS-485 Functionality
      2. 7.4.2 RS-232 Functionality
      3. 7.4.3 Mode Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.1 RS-485 Functionality

When the driver enable pin, DIR, is logic high, the differential outputs R2 and R1 follow the logic states at data input L3. A logic high at L3 causes R2 to turn high and R1 to turn low. If the differential output voltage defined as VOD = VR2 – VR1 is positive. When L3 is low, the output states reverse: R1 turns high, R2 becomes low, and VOD is negative.

When DIR is low, both outputs turn high-impedance. In this condition, the logic state at L3 is irrelevant. The DIR pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by default. The L3 pin has an internal pull-up resistor to VIO; thus, when left open while the driver is enabled, output R2 turns high and R1 turns low.

Table 7-4 Driver Function Table
INPUT ENABLE OUTPUTS FUNCTION
L3 DIR R2 R1
H H H L Actively drive bus high
L H L H Actively drive bus low
X L High impedance High impedance Driver disabled
X OPEN High impedance High impedance Driver disabled by default
OPEN H H L Actively drive bus high by default

Table 7-6 is valid for both half duplex and full duplex modes, and is independent of state of TERM_TX, TERM_RX and SLR pins.

In full duplex mode, if SHDN is high, receiver is always enabled. In half duplex mode, receiver is enabled is DIR = Low/floating and disabled if DIR = VIO. When the differential input voltage defined as VID = VR2 – VR1 or VR3 – VR4 is higher than the positive input threshold, VTH+, the receiver output, L2, turns high. When VID is lower than the negative input threshold, VTH-, the receiver output, L2, turns low. If VID is between VTH+ and VTH- the output is indeterminate.

In half duplex mode, when DIR is high, the receiver output is high-impedance and the magnitude and polarity of VID are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).

Table 7-7 is valid irrespective of state of TERM_TX, TERM_RX and SLR pins. Other logic output L1 remains high in RS-485 mode.

Table 7-5 Receiver Function Table
DIFFERENTIAL INPUT OUTPUT FUNCTION
VID = VR2 – VR1(Half duplex mode) or VR3 – VR4(Full duplex mode) L2
VTH+ < VID H Receive valid bus high
VTH- < VID < VTH+ ? Indeterminate bus state
VID < VTH- L Receive valid bus low
X High impedance for DIR = VIO in Half duplex mode Receiver disabled in half duplex mode for DIR = VIO
Open-circuit bus H Fail-safe high output
Short-circuit bus H Fail-safe high output
Idle (terminated) bus H Fail-safe high output