JAJSDR6C August 2017 – February 2022 TIC12400-Q1
PRODUCTION DATA
After the device enters TW condition, if the junction temperature continues to rise and goes above the temperature shutdown threshold (TTSD), the TIC12400-Q1 enters the Temperature Shutdown (TSD) condition and performs the following operations:
The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the INT_STAT register has been read during CS low. The TIC12400-Q1 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above TTSD - THYS. The status bit TSD_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature shutdown condition exists.
When the temperature drops below TTSD - THYS, the INT pin is asserted low (if released previously) to notify the microcontroller that the temperature shutdown condition no longer exists. The TSD bit of the interrupt register INT_STAT is flagged logic 1. In the IN_STAT_MISC register, the TSD_STAT bit is de-asserted back to logic 0, while the TW_STAT bit stays at logic 1. The device resumes operation using the wetting current setting described in section Temperature Warning if the temperature stays above TTW - THYS. Note: the polling restarts from the first enabled channel and the SSC interrupt is generated at the end of the first polling cycle. The detected switch status from the first polling cycle becomes the default switch status for subsequent polling.