JAJSDR6C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

Over operating free-air temperature range, VS = 4.5 V to 35 V, and VDD = 3 V to 5.5 V (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLY
IS_CONTContinuous mode VS power supply currentContinuous mode, IWETT= 10 mA, all switches open, no active ADC conversion or comparator comparison, no unserviced interrupt5.67mA
IS_POLL_COMP_25Polling mode VS power supply average current in comparator modeTA= 25°Polling mode, tPOLL= 64 ms, tPOLL_ACT= 128 µs, all 24 channels active and configured to comparator mode, all switches open, IWETT= 10 mA, no unserviced interrupt68100µA
IS_POLL_COMP_85TA= -40° to 85°C68110µA
IS_POLL_COMPTA= -40° to 125°C68170µA
IS_POLL_ADC_25Polling mode VS power supply average current in ADC modeTA= 25°Polling mode, tPOLL= 64 ms, tPOLL_ACT= 128 µs, all 24 channels active and configured to ADC mode, all switches open, IWETT= 10 mA, no unserviced interrupt75105µA
IS_POLL_ADC_85TA= -40° to 85°C75120µA
IS_POLL_ADCTA= -40° to 125°C75180µA
IS_RESETReset mode VS power supply currentReset mode, VRESET= VDD. VS= 12 V, all switches open, TA=25°C1217µA
IS_IDLE_25VS power supply average current in idle stateTRIGGER bit in CONFIG register = logic 0, TA= 25°C, no unserviced interrupt5075µA
IS_IDLE_85TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 85°C, no unserviced interrupt5095µA
IS_IDLETRIGGER bit in CONFIG register = logic 0, TA= -40°C to 125°C, no unserviced interrupt50145µA
IDDLogic supply current from VDDSCLK = SI = 0 V, CS = INT = VDD, no SPI communication1.510µA
VPOR_RPower on reset (POR) voltage for VSThreshold for rising VS from device OFF condition resulting in INT pin assertion and a flagged POR bit in the INT_STAT register3.854.5V
VPOR_FThreshold for falling VS from device normal operation to reset mode and loss of SPI communication1.952.8V
VOV_ROver-voltage (OV) condition for VSThreshold for rising VS from device normal operation resulting in INT pin assertion and a flagged OV bit in the INT_STAT register3540V
VOV_HYSTOver-voltage (OV) condition hysteresis for VS13.5V
VUV_RUnder-voltage (UV) condition for VSThreshold for rising VS from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register3.854.5V
VUV_FThreshold for falling VS from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register3.74.4V
VUV_HYSTUnder-voltage (UV) condition hysteresis for VS(1)75275mV
VDD_FThreshold for falling VDD resulting in loss of SPI communication2.52.9V
VDD_HYSTValid VDD voltage hysteresis50150mV
WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤ 100Ω , MINIMUM RESISTANCE VALUE WITH SWITCH OPEN ≥ 5000 Ω)
IWETT (CSO)Wetting current accuracy for CSO (switch closed)1 mA setting4.5 V ≤ VS ≤ 35 V0.8411.14mA
2 mA setting1.7122.32
5 mA setting4.5 V ≤ VS < 5 V2.395.5
5 V ≤ VS ≤ 35 V4.355.6
10 mA setting4.5 V ≤ VS < 6 V2.411
6 V ≤ VS ≤ 35 V8.41011.4
15 mA setting4.5 V ≤ VS < 6.5 V2.416.5
6.5 V ≤ VS ≤ 35 V12.51517
IWETT (CSI)Wetting current accuracy for CSI (switch closed)1 mA setting4.5 V ≤ VS ≤ 35 V0.751.12.05mA
2 mA setting1.62.23.3
5 mA setting4.35.67.1
10 mA setting9.211.513.4
15 mA setting4.5 V ≤ VS < 6 V1116.519.2
6 V ≤ VS ≤ 35 V13.716.519.2
VCSI_DROP_OPENVoltage drop from INx pin to AGND across CSI (switch open)10 mA setting, RSW= 5 kΩ4.5 V ≤ VS ≤ 35 V1.7V
15 mA setting, RSW= 5 kΩ1.7
VCSI_DROP_CLOSEDVoltage drop from INx pin to ground across CSI (switch closed)2 mA setting, IIN= 1 mA (4.5V ≤ VS ≤ 35V)4.5 V ≤ VS ≤ 35 V1.2V
5 mA setting, IIN= 1mA or 2 mA1.3V
10 mA setting, IIN= 1 mA, 2 mA, or 5 mA1.5V
15 mA setting, IIN= 1 mA, 2 mA, 5 mA, or 10 mA2.1V
WETTING CURRENT ACCURACY (ANALOG SWITCHES)
IWETTWetting current accuracy1 mA setting4.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 2.5 V0.8811.13mA
2 mA setting1.822.25
5 mA setting5.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 2.5 V4.355.5
5.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 3 V4.555.5
10 mA setting6 V ≤ VS ≤ 35 V, VS – VINX ≥ 4 V91011
15 mA setting6.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 5 V12.51516.5
LEAKAGE CURRENTS
IIN_LEAK_OFFLeakage current at input INx when channel is disabled0 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0)-45.3µA
IIN_LEAK_OFF_250 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0), TA = 25°C-0.50.5
IIN_LEAK_0mALeakage current at input INx when wetting current setting is 0mA0 V ≤ VINx ≤ 6 V, 6 V ≤ VS ≤ 35 V , IWETT setting = 0 mA-110110µA
µA
IIN_LEAK_LOSS_OF_GNDLeakage current at input INx under loss of GND conditionVS = 24 V, 0 V ≤ VINx ≤ 24 V, all grounds (AGND, DGND, and EP) = 24 V, VDD shorted to the grounds(1)-5µA
IIN_LEAK_LOSS_OF_VSLeakage current at input INx under loss of VS condition0 V ≤ VINx ≤ 24 V, VS shorted to the grounds = 0 V, VDD = 0 V5µA
LOGIC LEVELS
V/INT_LINT output low voltageI/INT = 2 mA0.35V
I/INT = 4 mA0.6
VSO_LSO output low voltageISO = 2 mA0.2VDDV
VSO_HSO output high voltageISO = -2 mA0.8VDDV
VIN_LSI, SCLK, and CS input low voltage0.3VDDV
VIN_HSI, SCLK, and CS input high voltage0.7VDDV
VRESET_LRESET input low voltage0.8V
VRESET_HRESET input high voltage1.6V
RRESET_25RESET pin internal pull-down resistorVRESET= 0 to 5.5 V, TA =25°C0.851.251.7MΩ
RRESETVRESET= 0 to 5.5 V, TA = –40° to 125°C0.22.1
SWITCH INPUT AND VS MEASUREMENT CONVERSION PARAMETERS
RESResolution10Bits
VOFFSETADC Offset error0 mA setting–101LSB
VFSEADC Full-scale error0 mA setting–10010LSB
OUTSWSwitch input conversion output1 mA setting4.5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx121726LSB
4.5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx425164
4.5 V ≤ VS ≤ 35 V, 600 Ω resistance to ground at INx87102122
2 mA setting4.5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx283445LSB
4.5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx89102122
4.5 V ≤ VS ≤ 35 V, 600 Ω resistance to ground at INx181205236
5 mA setting5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx7285105LSB
5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx223256296
5 V ≤ VS ≤ 35 V, 600 Ω resistance to ground at INx393512620
10 mA setting6 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx142171202LSB
6 V ≤ VS ≤ 35 V, 250 Ω resistance to ground at INx333427486
6 V ≤ VS ≤ 35 V, 400 Ω resistance to ground at INx430683823
15 mA setting6.5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx166256301LSB
6.5 V ≤ VS ≤ 35 V, 200 Ω resistance to ground at INx325512582
6.5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx450768879
OUTVSVS measurement output tolerance to full-scale rangeVS measurements (VS ≥ 4.5 V), VS_RATIO= 0 in register CONFIG±2%
VS measurements (VS ≥ 4.5 V), VS_RATIO= 1 in register CONFIG±2%
VFSRInput full-scale rangeINx measurements6V
VS measurements (VS ≥ 4.5 V), VS_RATIO= 0 in register CONFIG9
VS measurements (VS ≥ 4.5 V), VS_RATIO= 1 in register CONFIG30
RIN, SCInput resistanceINx measurements240kΩ
ADC Equivalent input resistance, VS above 7 VInput switch measurement, ILOAD= 30 µA135234356kΩ
RIN, COMPADC Equivalent input resistance, VS above 7 VTHRES_COMP Setting = 2 V88130172kΩ
THRES_COMP Setting = 2.7 V85126170
THRES_COMP Setting = 3 V73105137
THRES_COMP Setting = 4 V6895124
RRATIOInput voltage divider factor(1)INx measurements2-
VS measurements (VS ≥ 4.5 V), VS_RATIO = 0 in register CONFIG3-
VS measurements (VS ≥ 4.5 V), VS_RATIO = 1 in register CONFIG10-
COMPARATOR PARAMETERS
VTH_ COMP_2VComparator threshold for 2 VTHRES_COMP = 2 V1.852.25V
VTH_ COMP_2p7VComparator threshold for 2.7 VTHRES_COMP = 2.7 V2.42.9V
VTH_ COMP_3VComparator threshold for 3 VTHRES_COMP = 3 V2.853.3V
VTH_ COMP_4VComparator threshold for 4 VTHRES_COMP = 4 V3.74.35V
VS_COMPMinimum VS requirement for proper detectionTHRES_COMP = 2 V4.5V
THRES_COMP = 2.7 V5
THRES_COMP = 3 V5.5
THRES_COMP = 4 V6.5
RIN, COMPComparator equivalent input resistanceTHRES_COMP = 2 V30130kΩ
THRES_COMP = 2.7 V35130
THRES_COMP = 3 V35105
THRES_COMP = 4 V4395
(1) Verified by design.