JAJSDR6C August   2017  – February 2022 TIC12400-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.3.4 Wetting Current Diagnostic

When the TIC12400-Q1 is used to monitor safety-critical switches, it may be valuable for the microcontroller to have knowledge of the operating status of the wetting current sources and sinks. This can be achieved by activating the wetting current diagnostic feature provided for inputs IN0 to IN3. IN0 and IN1 can be diagnosed for defective wetting current sources, while IN2 and IN3 can be diagnosed for defective current sinks.

The wetting current diagnostic feature can be activated by setting the WET_D_INx_EN bits in the CONFIG register to 1 for the desired inputs, where x can be 0, 1, 2, or 3. If activated, the TIC12400-Q1 checks the status of the wetting current sources and sinks for the configured input periodically as part of the polling sequence. If the wetting current is determined to be flawed, the TIC12400-Q1 pulls the INT pin low to notify the host and flag the WET_DIAG bit in the INT_STAT register to logic 1. The OI bit in the SPI flag is also asserted during SPI transactions. The microcontroller can then read bits IN0_D to IN3_D in register IN_STAT_MISC to learn more information on which wetting current source/sink is defective.

The wetting current diagnostic is not performed for inputs that are disabled (IN_EN_x bit = 0 in the IN_EN register) from polling, even if the feature is activated for those inputs. Also, it is critical to configure the current source/sink appropriately (CSO for IN0 and IN1, and CSI for IN2 and IN3) and program the input to ADC input mode before activating the wetting current diagnostic feature to prevent false interrupts from being generated. The wetting current diagnostic feature can be performed regardless of the states of external switches, and it is available in both continuous mode and polling mode.

Figure 8-21 shows an example of the feature carried out in a typical polling sequence. In this example, it can be observed that the wetting current is activated for duration of tPOLL_ACT+ tADC for each input diagnosed (IN0 or IN2). Normal polling sequence resumes with IN4 and the wetting current is activated for tPOLL_ACT for the rest of the inputs. The diagnostic is not executed on inputs IN1 and IN3 in this example since they are disabled.

GUID-C3643494-7688-48AA-9DCD-ECEA33D9E0BD-low.gifFigure 8-21 An Example of the Polling Sequence in Standard Polling Mode With Wetting Current Diagnostic Enabled