SLLSFS6A September   2024  – December 2024 TIOL221

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Wake-Up Detection
      2. 7.3.2  Current Limit Configuration
        1. 7.3.2.1 Current Limit Configuration in Pin-Mode
        2. 7.3.2.2 Current Limit Configuration in SPI mode
      3. 7.3.3  CQ Current Fault Detection, Indication and Auto Recovery
      4. 7.3.4  DO Current Fault Detection, Indication and Auto Recovery
      5. 7.3.5  CQ and DI Receivers
      6. 7.3.6  Fault Reporting
        1. 7.3.6.1 Thermal Warning, Thermal Shutdown
      7. 7.3.7  The Integrated Voltage Regulator (LDO)
      8. 7.3.8  Reverse Polarity Protection
      9. 7.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 7.3.10 Undervoltage Lock-Out (UVLO)
      11. 7.3.11 Interrupt Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 CQ and DO Tracking mode
    5. 7.5 SPI Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Driving Capacitive Loads
        2. 8.2.2.2 Driving Inductive Loads
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 TIOL221 Registers
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 RGE (VQFN), 24-Pin
(Top View)
Figure 4-2 YAH (DSBGA), 25-Pin
(Top View, Bumps Down)
Table 4-1 Pin Functions
PIN NAMEPIN NUMBERI/OTYPEDESCRIPTION
VQFNDSBGA
CQ8A1I/OHigh VoltageIO-link signal data pin.
CS/PP1E1IDigitalChip select input pin in the SPI-mode.

Push-pull mode selection input in pin-mode

DI12A5IHigh VoltageDI receiver Input. DI receiver output can be monitored at the RX2 pin.
DO11A4OHigh VoltageDO driver output. DO is the inverse logic level of the input at the TX2 pin.
EN13C2ILow voltage DigitalCQ driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak internal pull-down.
EN219E5ILow voltage DigitalDO driver enable input signal from the local controller. Logic low sets the DO output at Hi-Z. Weak internal pull-down.
ILIM_ADJ16B2ILow voltage AnalogInput for the current limit adjustment for the CQ driver. Connect resistor RSET1 between ILIM_ADJ1 and LM.
ILIM_ADJ27B3ILow voltage AnalogInput for the current limit adjustment for the DO driver. Connect resistor RSET2 between ILIM_ADJ2 and LM.
INT/NFLT120E4OLow voltage DigitalInterrupt output, push-pull (SPI-mode) or fault indicator for CQ channel, open-drain (pin-mode)
LM10A3GGroundGround.
LP9A2PIHigh VoltagePower supply input (24V typical) to the device. Connect 1µF capacitor to LM (ground) as close to the device as possible.
NC--C3NCNo ConnectNot connected internally.
RX12D1OLow voltage DigitalC/Q Receiver Logic Output. RX2 is the inverse logic level of the signal on the CQ input.
RX215C5OLow voltage DigitalDI Receiver Logic Output. RX2 is the inverse logic level of the signal on the DI input.
SCK22E3ILow voltage DigitalSPI clock input
SDI/NPN24E2ILow voltage DigitalSPI serial data input (SPI-mode)

Or NPN mode selector (pin-mode)

SDO/NFLT221D3OLow voltage DigitalSPI serial data output, push-pull (SPI-mode) or fault inductor for DO channel, open-drain (pin-mode)
SPI/PIN23D2ILow voltage DigitalSPI or pin-mode selection input. Drive this pin low for pin-mode operation. Drive this pin high for SPI-mode control.
TX14C1ILow voltage DigitalCQ driver input data from local microcontroller. Weak internal pull-up.
TX217D5ILow voltage DigitalDO driver input data from local microcontroller. Weak internal pull-up.
VOUT13B4POLow voltageLDO regulator output. Output level determined by VSEL pin
VSEL16C4ILow voltage
  • Connect to GND for 3.3V LDO output with LP as the LDO input supply
  • Connect to VOUT for 5V LDO output with LP as the LDO input supply
  • Leave the pin floating for 3.3V LDO output with V5IN as the LDO input supply
RESET14B1

O

Low voltageReset output pin, open-drain, active low. The pin behaves as a reset pin to indicate UV on LP or VOUT.
V5IN5B5PILow voltage(Optional) Connect this pin 5V supply input from external regulator to reduce the power dissipation from the internal regulator. Leave the pin floating if unused.
WU18D4OLow voltage DigitalWake-up indicator to the local microcontroller. Open-drain output, connect this pin via pull-up resistor to VOUT.
Thermal PadThermal PadN/AGGroundConnect the exposed thermal pad to ground (LM) for optimal thermal and electrical performance