JAJSVB5
September 2024
TIOL221
ADVANCE INFORMATION
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
ESD Ratings - IEC Specifications
5.4
Recommended Operating Conditions
5.5
Thermal Information
5.6
Electrical Characteristics
5.7
Switching Characteristics
6
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagrams
7.3
Feature Description
7.3.1
Wake-Up Detection
7.3.2
Current Limit Configuration
7.3.2.1
Current Limit Configuration in Pin-Mode
7.3.2.2
Current Limit Configuration in SPI mode
7.3.3
CQ Current Fault Detection, Indication and Auto Recovery
7.3.4
DO Current Fault Detection, Indication and Auto Recovery
7.3.5
CQ and DI Receivers
7.3.6
Fault Reporting
7.3.6.1
Thermal Warning, Thermal Shutdown
7.3.7
The Integrated Voltage Regulator (LDO)
7.3.8
Reverse Polarity Protection
7.3.9
Integrated Surge Protection and Transient Waveform Tolerance
7.3.10
Undervoltage Lock-Out (UVLO)
7.3.11
Interrupt Function
7.4
Device Functional Modes
7.4.1
CQ and DO Tracking mode
7.5
SPI Programming
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Driving Capacitive Loads
8.2.2.2
Driving Inductive Loads
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
TIOL221 Registers
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
サポート・リソース
10.3
Trademarks
10.4
静電気放電に関する注意事項
10.5
用語集
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Tape and Reel Information
12.2
Mechanical Data
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RGE|24
サーマルパッド・メカニカル・データ
発注情報
jajsvb5_oa
7.2
Functional Block Diagrams
Figure 7-1
Block Diagram