JAJSVB5A September   2024  – December 2024 TIOL221

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Wake-Up Detection
      2. 7.3.2  Current Limit Configuration
        1. 7.3.2.1 Current Limit Configuration in Pin-Mode
        2. 7.3.2.2 Current Limit Configuration in SPI mode
      3. 7.3.3  CQ Current Fault Detection, Indication and Auto Recovery
      4. 7.3.4  DO Current Fault Detection, Indication and Auto Recovery
      5. 7.3.5  CQ and DI Receivers
      6. 7.3.6  Fault Reporting
        1. 7.3.6.1 Thermal Warning, Thermal Shutdown
      7. 7.3.7  The Integrated Voltage Regulator (LDO)
      8. 7.3.8  Reverse Polarity Protection
      9. 7.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 7.3.10 Undervoltage Lock-Out (UVLO)
      11. 7.3.11 Interrupt Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 CQ and DO Tracking mode
    5. 7.5 SPI Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Driving Capacitive Loads
        2. 8.2.2.2 Driving Inductive Loads
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 TIOL221 Registers
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

6 Parameter Measurement Information

TIOL221 Test Circuit for Driver SwitchingFigure 6-1 Test Circuit for Driver Switching
TIOL221 Waveforms for Driver Output Switching MeasurementsFigure 6-2 Waveforms for Driver Output Switching Measurements
TIOL221 Waveforms for Driver Enable or Disable Time MeasurementsFigure 6-3 Waveforms for Driver Enable or Disable Time Measurements
TIOL221 Test Circuit for Receiver SwitchingFigure 6-4 Test Circuit for Receiver Switching
TIOL221 Receiver Switching MeasurementsFigure 6-5 Receiver Switching Measurements
TIOL221 Overcurrent and Wake Conditions for EN = H and ILIM_ADJ = 10kΩ to 110kΩ,TX = H (Full Lines); and TX = L (Red Dotted Lines)Figure 6-6 Overcurrent and Wake Conditions for EN = H and ILIM_ADJ = 10kΩ to 110kΩ,
TX = H (Full Lines); and TX = L (Red Dotted Lines)
TIOL221 Overcurrent and Wake Conditions for EN = H and ILIM_ADJ is floating, TX = H (Full Lines); and TX = L (Red Dotted Lines)Figure 6-7 Overcurrent and Wake Conditions for EN = H and ILIM_ADJ is floating, TX = H (Full Lines); and TX = L (Red Dotted Lines)
TIOL221 SPI Read/Write Timing CharacteristicsFigure 6-8 SPI Read/Write Timing Characteristics
TIOL221 Driving the Inductive LoadFigure 6-9 Driving the Inductive Load
TIOL221 Driving the Capacitive LoadFigure 6-10 Driving the Capacitive Load
TIOL221 Interrupt Pin Toggling Behavior (SPI Mode; INT_TOG = 1b)Figure 6-11 Interrupt Pin Toggling Behavior (SPI Mode; INT_TOG = 1b)