JAJSVB5 September   2024 TIOL221

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 ESD Ratings - IEC Specifications
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Wake-Up Detection
      2. 7.3.2  Current Limit Configuration
        1. 7.3.2.1 Current Limit Configuration in Pin-Mode
        2. 7.3.2.2 Current Limit Configuration in SPI mode
      3. 7.3.3  CQ Current Fault Detection, Indication and Auto Recovery
      4. 7.3.4  DO Current Fault Detection, Indication and Auto Recovery
      5. 7.3.5  CQ and DI Receivers
      6. 7.3.6  Fault Reporting
        1. 7.3.6.1 Thermal Warning, Thermal Shutdown
      7. 7.3.7  The Integrated Voltage Regulator (LDO)
      8. 7.3.8  Reverse Polarity Protection
      9. 7.3.9  Integrated Surge Protection and Transient Waveform Tolerance
      10. 7.3.10 Undervoltage Lock-Out (UVLO)
      11. 7.3.11 Interrupt Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 CQ and DO Tracking mode
    5. 7.5 SPI Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Driving Capacitive Loads
        2. 8.2.2.2 Driving Inductive Loads
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 TIOL221 Registers
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information
    2. 12.2 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

5.6 Electrical Characteristics

Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical values are at LP = 24 V, VVOUT = 3.3 V and TA = 25 ℃ unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (LP)
I(LP-SHDN) Supply quiescent current in shutdown mode CQ TX and RX, DO and DI are disabled. No load on VOUT. SPI mode only 1.2 2.1 mA
I(LP-RX-ONLY) Supply current when only inputs are enabled CQ and DO are disabled. CQ RX and DI are enabled. No load on VOUT.
RSETx >= 10kΩ (current limit < 500mA) , EN1=EN2=L		 CQ and DO are disabled. CQ RX and DI are enabled. No load on VOUT 1.4 2.5 mA
I(LP-CQ-DO) Quiescent supply current when both CQ and DO are enabled. V5IN supplied externally RSETx >= 10kΩ. TX1=TX2=H, No load on CQ or DO, Push-pull or NPN mode only 3.1 4 mA
I(LP-CQ-DO) RSETx >= 10kΩ. TX1=TX2=L, No load on CQ or DO 4.7 5.5 mA
V(LP-UVLO) LP under voltage lockout LP falling; NFAULT = Hi-Z LP falling; NFAULT = Hi-Z 6 6.3 V
V(LP-UVLO) LP under voltage lockout LP rising; NFAULT = LOW LP rising; NFAULT = LOW 6.5 6.8 V
V(LP-UVLO,HYS) LP under voltage hysteresis Rising to falling threshold Rising to falling threshold 200 mV
V(LPW) LP undervoltage warning LP falling 14 16 18 V
V(LPW-HYS) LP undervoltage warning hysteresis 530 mV
V5IN
V5IN(UVLO,F) Falling UVLO level for V5IN V5IN Falling 3.4 3.5 3.6 V
V5IN(UVLO,R) Rising UVLO level for V5IN V5IN Rising 3.7 3.8 4.0 V
I5_IN Input supply current at 5VIN  CQ and DO disabled, No load on VOUT 0.15 1 mA
LINEAR REGULATOR (VOUT)
V(VOUT) Voltage regulator output VOUT set to 5 V 4.75 5 5.25 V
VOUT set to 3.3 V 3.13 3.3 3.46 V
LINEREGVOUT Line regulation (dV(VOUT)/dV(LP)) I(VCC_OUT) = 1 mA
V(LP) = 7 V to 36 V (VOUT = 5 V)
V(LP) = 7 V to 36 V OR V5IN = 4.5 to 5.5 V (VOUT = 3.3 V)		 1.7 mV/V
LOADREGVOUT Load regulation (dV(VOUT)/V(OUT)) V(LP) = 24 V for VOUT=5V
V(LP) = 24 V or V5IN= 5V for VOUT=3.3 V
I(VCC_OUT) = 100 µA to 20 mA		 1 %
UVVOUT5F Falling UV threshold on VOUT (5V setting) VSEL connected to VOUT, VOUT falling 3.4 3.6 3.8 V
UVVOUT5R Rising UV threshold on VOUT (5V setting) VSEL connected to VOUT, VOUT rising 3.6 3.8 4.0 V
UVVOUT3F Falling UV threshold on VOUT (3.3V setting) VSEL connected to GND or Floating(V5IN supplied), VOUT falling 2.5 2.7 2.9 V
UVVOUT3R Rising UV threshold on VOUT (3.3V setting) VSEL connected to GND or Floating(V5IN supplied), VOUT rising 2.6 2.8 3.0 V
PSSR Power Supply Rejection Ratio 100 kHz, I(VCC_OUT) = 20 mA 40 dB
DRIVER OUTPUT (CQ, DO)
RDSON-HS High-side driver on-resistance ILOAD = 200 mA, Current Limit = 300 mA 2.5 4.5 Ω
RDSON-LS Low-side driver on-resistance ILOAD = 200 mA, Current Limit = 300 mA 2.5 4.5 Ω
IO(LIM) Driver output current limit SPI/PIN = LOW 
V(DRIVER)= (VLP - 3) V or 3V, 		 RSETx = 110 kΩ 35 55 70 mA
RSETx = 10 kΩ 300 350 400 mA

RSETx = 0 to 5 kΩ
 		 500 mA

RSETx = OPEN
 		 260 330 400 mA
IO(LIM) Driver output current limit SPI/PIN = HIGH,
V(DRIVER)= (VLP - 3) V or 3V, 		 3h[7:6]= 0h 35 60 75 mA
3h[7:6]= 1h 50 75 95 mA
3h[7:6]= 2h 100 140 175 mA
3h[7:6]= 3h 150 190 260 mA
3h[7:6]= 4h 200 230 330 mA
3h[7:6] = 5h 250 290 410 mA
3h[7:6] = 6h 300 350 485 mA
3h[7:6]= 7h 500 700 mA
IOZ(CQ) CQ leakage EN1 = LOW, 0 ≤ V(CQ) ≤ (V(LP) - 0.1 V) –2 2 µA
ILLM(CQ) CQ load discharge current EN1 = LOW, RSET1 = 0 to 5 kΩ (1), V(CQ) >= 5 V 5 8.5  15 mA
ILLM(DO) DO load discharge current EN2 = LOW, RSET2  = 0 to 5 kΩ; V(DO) >= 5 V 5 8.5  15 mA
IPU-DO DO driver weak pull-up current  SPI/PIN=HIGH, EN2=LOW,  TX2=HIGH, RSET2: 10 kΩ to 110 kΩ  AND Weak pull-up enabled (SPI mode only)
0 ≤ V(DO) ≤ (V(LP) - 2 V)		 40 50 80 µA
IPD-DO DO driver weak pull-down current (SPI/PIN=HIGH, EN2=LOW, TX2=LOW, RSET2: 10 kΩ to 110 kΩ 
 AND Weak pull-up enabled (SPI mode only)		 2 ≤ V(DO) ≤ V(LP) 40 50 80 µA
IPU-CQ CQ driver weak pull-up current  Driver disabled, Weak pull-up enabled (SPI mode)
 		 0 ≤ V(CQ) ≤ (V(LP) - 2 V) 40 50 80 µA
IPD-CQ CQ driver weak pull-down current Driver disabled, Weak pull-down enabled (SPI mode) 2 ≤ V(CQ) ≤ V(LP)  40 50 80 µA
RECEIVER INPUT (CQ, DI)
V(THH) Input threshold “H” V(LP) > 18 V, EN= LOW 10.5 13 V
V(THL) Input threshold “L" 8 11.5 V
V(HYS) Receiver Hysteresis
(V(THH) - V(THL))		 0.75 V
V(THH) Input threshold “H” V(LP) < 18 V, EN= LOW See Note (2) See Note (3) V
V(THL) Input threshold “L" V(LP) < 18 V, EN= LOW See Note (4) See Note (5) V
V(HYS) Receiver Hysteresis
(V(THH) - V(THL))		 0.75 V
CIN-CQ CQ input capacitance CQ driver disabled, weak pull-up/pull-down disabled, f =100kHz 150 pF
CIN-DI DI input capacitance  f =100kHz  100 pF
IPU-DI DI weak pull-up current  SPI Mode, Weak pull-up enabled on DI pin
0 ≤ V(DI) ≤ (V(LP) - 2 V)		 40 50 80 µA
IPD-DI DI weak pull-down current SPI Mode, Weak pull-down enabled on DI pin 2 ≤ V(DI) ≤ V(LP)  40 50 80 µA
LOGIC-LEVEL INPUTS (CS/PP, SCK, SDI/NPN, SPI/PIN, EN1, EN2, TX1, TX2, VSEL)
VIL Input logic low voltage 0.3*VOUT V
VIH Input logic high voltage 0.7*VOUT V
RPD Pull-down resistance at EN1, EN2, SDI/NPN, SCK 100 kΩ
RPU Pull-up resistance at TX1, TX2, , CS/PP, SPI/PIN 100 kΩ
RPU Pull-up resistance at VSEL 1000 kΩ
LOGIC-LEVEL OUTPUTS (WU, SDO/NFLT2, INT/NFLT1, RX1, RX2, RESET)
VOH Output logic high voltage RX1, RX2, SDO, INT IO = 4 mA IO = 4 mA VOUT-0.5 V
VOL Output logic low voltage IO = 4 mA 0.4 V
IOZ Output high impedance leakage at NFLT1, NFLT2, WU, RESET Output in Hi-Z, VO = 0 V or VCC_IN/OUT –1 1 µA
PROTECTION CIRCUITS
T(WRN) Thermal warning Die temperature TJ 125 °C
T(SDN) Thermal shutdown 150 160 °C
T(HYS) Thermal hysteresis for shutdown 14 °C
T(WRN) Thermal hysteresis for warning Die temperature TJ Die temperature TJ 14 °C
IREV CQ Leakage current in reverse polarity  EN=LOW, TX=x; LP= 24 V  VCQ = (V(LP) -36V) OR   V(CQ) = (V(LP) +36V) 60 µA
EN=LOW, TX=x; LP= 24 V  VCQ = (V(LP) -65V) OR   V(CQ) = 65V 110 µA
EN = HIGH, TX = LOW; V(CQ to LP) = 3 V, RSET  >= 10 kΩ 650 µA
EN = HIGH, TX = HIGH; V(CQ to LM) = -3 V 10 µA
(1) Current fault indication and current fault auto recovery will be de-activated.
(2) VTHH (min) = 5 V + (11/18) [V(LP) - 8 V]
(3) VTHH (max) = 6.5 V + (13/18) [V(LP) - 8 V]
(4) VTHL (min) = 4 V + (8/18) [V(LP) -8 V]
(5) VTHL (max) = 6 V + (11/18) [V(LP) -8 V]