JAJSI95 December   2019 TL16C750E

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     ブロック図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. 7.1      ESD Ratings
    3. Table 2. Recommended Operating Conditions
    4. Table 3. Thermal Information
    5. Table 4. Electrical Characteristics
    6. Table 5. Timing Requirements
    7. 7.2      Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1  UART Modes
      2. 9.3.2  Trigger Levels
      3. 9.3.3  Hardware Flow Control
      4. 9.3.4  Auto-RTS
      5. 9.3.5  Auto-CTS
      6. 9.3.6  Software Flow Control
      7. 9.3.7  Software Flow Control Example
      8. 9.3.8  Reset
      9. 9.3.9  Interrupts
      10. 9.3.10 Interrupt Mode Operation
      11. 9.3.11 Polled Mode Operation
      12. 9.3.12 Break and Timeout Conditions
      13. 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
      14. 9.3.14 Fractional Divisor
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Interface Mode
        1. 9.4.1.1 IOR Used (MODE = VCC)
        2. 9.4.1.2 IOR Unused (MODE = GND)
      2. 9.4.2 DMA Signaling
        1. 9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)
        2. 9.4.2.2 Block DMA Transfers (DMA Mode 1)
      3. 9.4.3 Sleep Mode
    5. 9.5 Register Maps
      1. 9.5.1  Registers Operations
      2. 9.5.2  Receiver Holding Register (RHR)
      3. 9.5.3  Transmit Holding Register (THR)
      4. 9.5.4  FIFO Control Register (FCR)
      5. 9.5.5  Line Control Register (LCR)
      6. 9.5.6  Line Status Register (LSR)
      7. 9.5.7  Modem Control Register (MCR)
      8. 9.5.8  Modem Status Register (MSR)
      9. 9.5.9  Interrupt Enable Register (IER)
      10. 9.5.10 Interrupt Identification Register (IIR)
      11. 9.5.11 Enhanced Feature Register (EFR)
      12. 9.5.12 Divisor Latches (DLL, DLH, DLF)
      13. 9.5.13 Transmission Control Register (TCR)
      14. 9.5.14 Trigger Level Register (TLR)
      15. 9.5.15 FIFO Ready Register
      16. 9.5.16 Alternate Function Register (AFR)
      17. 9.5.17 RS-485 Mode
      18. 9.5.18 IrDA Overview
      19. 9.5.19 IrDA Encoder Function
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Set the desired baud rate
        2. 10.2.2.2 Reset the fifos
        3. 10.2.2.3 Sending data on the bus
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.5.1 Registers Operations

Each register is selected using address lines A[0], A[1], A[2], and in some cases, bits from other registers. The programming combinations for register selection are shown in Figure 30.

TL16C750E register_map_SLLSF10.gif

NOTE:

MCR[7:5], FCR[5:4], and IER[7:4] can only be modified when EFR[4] is set.
Figure 30. Register Map – Read and Write Properties

Table 13 lists and describes the TL16C750E internal registers.

Table 13. TL16C750E Internal Registers(1)(2)

ADDRESS
[A2:A0]		 REGISTER R/W
(3) 		ACCESS CONSIDERATION BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
0 0 0 RHR R LCR[7] = 0 bit 7
0		 bit 6
0		 bit 5
0		 bit 4
0		 bit 3
0		 bit 2
0		 bit 1
0		 bit 0
0
THR W bit 7
0		 bit 6
0		 bit 5
0		 bit 4
0		 bit 3
0		 bit 2
0		 bit 1
0		 bit 0
0
DLL(5) RW LCR[7] = 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 0 1 IER RW LCR[7] = 0 CTS# Interrupt enable(1)
0		 RTS# Interrupt enable(1)
0		 Xoff Interrupt enable(1)
0		 Sleep mode(1)
0		 Modem status interrupt
0		 RX line status interrupt
0		 THR empty interrupt
0		 RX data available interrupt
0
DLH(5) RW LCR[7] = 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 1 0 IIR R LCR[7] = 0 FCR(0)
0		 FCR(0)
0		 CTS# / RTS#
0		 Xoff
0		 Interrupt priority bit 2
0		 Interrupt priority bit 1
0		 Interrupt priority bit 0
0		 Interrupt status
1
FCR W RX trigger level
0		 RX trigger level
0		 TX trigger level(1)
0		 TX trigger level(1)
0		 DMA mode select
0		 Resets TX FIFO
0		 Resets RX FIFO
0		 Enable FIFOs
0
AFR(4) RW LCR[7:5] = 100 DLY2
0		 DLY1
0		 DLY0
0		 RCVEN
1		 485LG
0		 485EN
0		 IREN
0		 RES
0
EFR(6) RW LCR[7:0] = 10111111 Auto CTS#
0		 Auto RTS#
0		 Special character detect
0		 Enable enhanced functions
0		 S/W flow control bit 3
0		 S/W flow control bit 2
0		 S/W flow control bit 1
0		 S/W flow control bit 0
0
0 1 1 LCR RW None DLAB & EFR enable
0		 Break control bit
0		 Sets parity
0		 Parity type select
1		 Parity enable
1		 No. of stop bits
1		 Word length
0		 Word length
1
1 0 0 MCR RW LCR[7:0] ≠ 10111111 1x / 4x clock(1)
0		 TCR & TLR enable(1)
0		 Xon any(1)
0		 Enable loopback
0		 INT enable
0		 FIFORDY enable
0		 RTS#
0		 DTR#
0
Xon1(6) RW LCR[7:0] = 10111111 bit 7
1		 bit 6
1		 bit 5
1		 bit 4
1		 bit 3
1		 bit 2
1		 bit 1
1		 bit 0
1
1 0 1 LSR R LCR[7:0] ≠ 10111111 Error in RX FIFO
0		 THR & TSR empty
1		 THR empty
1		 Break interrupt
0		 Framing error
0		 Parity error
0		 Overrun error
0		 Data in receiver
0
Xon2(6) RW LCR[7:0] = 10111111 bit 7
1		 bit 6
1		 bit 5
1		 bit 4
0		 bit 3
1		 bit 2
1		 bit 1
1		 bit 0
1
1 1 0 MSR R LCR[7:0] ≠ 10111111 & none of the below conditions are true CD#
1		 RI#
1		 DSR#
1		 CTS#
1		 CD#
0		 RI#
0		 DSR#
0		 CTS#
0
Xoff1(6) RW LCR[7:0] = 10111111 bit 7
1		 bit 6
1		 bit 5
1		 bit 4
1		 bit 3
1		 bit 2
1		 bit 1
1		 bit 0
1
TCR(7) RW EFR[4] = 1 & MCR[6] = 1 bit 7
0		 bit 6
0		 bit 5
0		 bit 4
0		 bit 3
0		 bit 2
0		 bit 1
0		 bit 0
0
1 1 1 SPR RW LCR[7:0] ≠ 10111111 & none of the below conditions are true bit 7
0		 bit 6
0		 bit 5
0		 bit 4
0		 bit 3
0		 bit 2
0		 bit 1
0		 bit 0
0
Xoff2(6) RW LCR[7:0] = 10111111 bit 7
1		 bit 6
1		 bit 5
1		 bit 4
1		 bit 3
1		 bit 2
1		 bit 1
1		 bit 0
1
TLR(7) RW EFR[4] = 1 & MCR[6] = 1 bit 7
0		 bit 6
0		 bit 5
0		 bit 4
0		 bit 3
0		 bit 2
0		 bit 1
0		 bit 0
0
DLF(9) RW LCR[7] = 1, LCR ≠ 0xBF, EFR[4] = 1, MCR ≠ 0bx1x0 x1xx (10) bit 7
0		 bit 6
0 (Reserved, RO)		 bit 5
0		 bit 4
0		 bit 3
0		 bit 2
0		 bit 1
0		 bit 0
0
FIFORdy(8) R MCR[4] = 0 & MCR[2] = 1 0 0 0 RX FIFO A status
0		 0 0 0 TX FIFO A status
0
(1) Bits represented by the blue shaded cells can only be modified if EFR[4] is enabled, that is, if enhanced functions are enabled.
(2) For more register access information, see Figure 30.
(3) Read = R; Write = W
(4) This register is only accessible LCR[7:5] = 100
(5) This register is only accessible when LCR[7] = 1
(6) This register is only accessible when LCR = 1011 1111 (0xBF)
(7) This register is only accessible when EFR[4] = 1 and MCR[6] = 1
(8) This register is accessible when any CS A-B = 0, MCR[2] = 1, and loopback MCR[4] = 0 is disabled.
(9) This register is accessible when LCR[7] = 1, LCR ≠ 0xBF, EFR[4] = 1, MCR ≠ 0bx1x0 x1xx(10)
(10) A 'x' denotes a do not care for a bit value