JAJSVH4C August   2006  – October 2024

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Reference Section Electrical Characteristics
    6. 5.6  Oscillator Section Electrical Characteristics
    7. 5.7  Error-Amplifier Section Electrical Characteristics
    8. 5.8  Current-Sense Section Electrical Characteristics
    9. 5.9  Output Section Electrical Characteristics
    10. 5.10 Undervoltage-Lockout Section Electrical Characteristics
    11. 5.11 Pulse-Width Modulator Section Electrical Characteristics
    12. 5.12 Supply Voltage Electrical Characteristics
    13. 5.13 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Functional Block Diagram
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Shutdown Technique
    3. 7.3 Open-Loop Laboratory Test Fixture
    4. 7.4 Typical Application
      1. 7.4.1 Application Curves
  9. 8 Device and Documentation Support
    1. 8.1 Related Links
    2. 8.2 Trademarks
    3. 8.3 静電気放電に関する注意事項
    4. 8.4 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2 Shutdown Technique

The PWM controller (see Figure 7-4) can be shut down by two methods: either raise the voltage at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE terminal is removed. In one example, an externally latched shutdown can be accomplished by adding an SCR that resets by cycling VCC below the lower UVLO threshold. At this point, the reference turns off, allowing the SCR to reset.

TL284xB TL384xB Shutdown TechniquesFigure 7-4 Shutdown Techniques

A fraction of the oscillator ramp can be summed resistively with the current-sense signal to provide slope compensation for converters requiring duty cycles over 50% (see Figure 7-5). Note that capacitor C forms a filter with R2 to suppress the leading-edge switch spikes.

TL284xB TL384xB Slope CompensationFigure 7-5 Slope Compensation