JAJSN47G February   2003  – August 2022 TLC2272-Q1 , TLC2272A-Q1 , TLC2274-Q1 , TLC2274A-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VDD = 5 V (TLC2272-Q1 and TLC2272A-Q1)
    6. 6.6 Electrical Characteristics: VDD± = ±5 V (TLC2272-Q1 and TLC2272A-Q1)
    7. 6.7 Electrical Characteristics: VDD = 5 V (TLC2274-Q1 and TLC2274A-Q1)
    8. 6.8 Electrical Characteristics: VDD± = ±5 V (TLC2274-Q1 and TLC2274A-Q1)
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Macromodel Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Differential Amplifier Equations
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 PSpice® for TI
        2. 9.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1 Layout Guidelines

The TLC227x-Q1 is a wideband amplifier. To realize the full operational performance of the device, good high frequency printed-circuit-board (PCB) layout practices are required. Low-loss 0.1-μF bypass capacitors must be connected between each supply pin and ground as close to the device as possible. The bypass capacitor traces must be designed for minimum inductance.