JAJSHO0J August   1983  – November 2023 TLC555

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I
    6. 5.6 Electrical Characteristics: VDD = 5 V
    7. 5.7 Electrical Characteristics: VDD = 15 V
    8. 5.8 Timing Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Monostable Operation
      2. 6.3.2 Astable Operation
      3. 6.3.3 Frequency Divider
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Missing-Pulse Detector
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Pulse-Width Modulation
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 Pulse-Position Modulation
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curves
      4. 7.2.4 Sequential Timer
        1. 7.2.4.1 Design Requirements
        2. 7.2.4.2 Detailed Design Procedure
        3. 7.2.4.3 Application Curve
      5. 7.2.5 Designing for Improved ESD Performance
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.3.2 Astable Operation

As shown in Figure 6-5, adding a second resistor, RB, to the circuit of Figure 6-2 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through RA and RB and then discharges through RB only. Therefore, the duty cycle is controlled by the values of RA and RB.

This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≈ 0.67 × VCC) and the trigger-voltage level (≈ 0.33 × VCC). As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.

GUID-F2CA5511-CC89-4D74-B8F8-FAEC5E54DCB5-low.gif
Decouple CONT voltage to ground with a capacitor to improve operation. Reevaluate for individual applications.
Figure 6-5 Circuit for Astable Operation
GUID-AB8E0CF0-8384-46CE-8B1A-06E94A62E03D-low.gif
RA = 5 kΩ RB = 3 kΩ C = 0.15 µF
See Figure 6-5
Figure 6-6 Typical Astable Waveforms

Figure 6-6 shows typical waveforms generated during astable operation. The output high-level duration tH and low-level duration tL for frequencies below 100 kHz can be calculated as follows:

Equation 1. GUID-79EE162E-2D50-4A0F-89EC-D2985AD3DFC6-low.gif
Equation 2. GUID-871606B6-340E-4997-8BCE-D9213A15C336-low.gif

Other useful relationships are shown below:

Equation 3. GUID-44FC7B0B-A3ED-4854-B29F-A2CFB1987145-low.gif
Equation 4. GUID-B97C499F-6824-4217-9587-1A8C5E0E06C7-low.gif
Equation 5. GUID-92AE6D47-8A9B-46A8-8660-AA1F6620B351-low.gif
Equation 6. GUID-92C335DA-25E7-4FD9-9877-616CDC9622DD-low.gif
Equation 7. GUID-6D1D9605-BD3E-42BB-A84A-C7E4CF33E4A0-low.gif

Equation 1 to Equation 7 do not account for any propagation delay times from the TRIG and THRES inputs to DISCH output. These delay times add directly to the period and overcharge the capacitor, which creates differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance ron during discharge adds to RB to provide another source of timing error in the calculation when RB is very low. The following equations provide better agreement with measured values. The formulas in Equation 8 represent the actual low and high times when used at higher frequencies (beyond 100 kHz) because propagation delay and discharge on resistance is added to the formulas. The value of CT includes both the nominal or deliberate timing capacitance, as well as parasitic capacitance on the PCB. Decoupling capacitance on CONT also affects the duty cycle, with an error contribution that depends on the capacitor leakage resistance. For additional discussion, see the Design low-duty-cycle timer circuits article.

Equation 8. GUID-5B8B46E0-F78A-4ED1-A060-8DB1659392FB-low.gif

These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between ln(2) at low frequencies, and ln(3) at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted with good results. Output waveform duty cycles less than 50% require that tc(H) / tc(L) < 1 and possibly that RA ≤ ron. These conditions can be difficult to obtain. Figure 6-8 shows the nominal free-running frequency associated with various combinations of CT and RA + 2 × RB.

GUID-6CE66626-D3DC-4084-B2DE-96D66016B8DE-low.gifFigure 6-7 Trigger and Threshold Voltage Waveform
GUID-B6373871-80AC-4174-AB79-9FAEC203B24D-low.gifFigure 6-8 Nominal Free-Running Frequency vs Timing Capacitance
Resistance = RA + 2 × RB