SCLS715A March   2009  – November 2015 TLC59208F

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power-On Reset
      2. 9.3.2 External Reset
      3. 9.3.3 Software Reset
      4. 9.3.4 Individual Brightness Control With Group Dimming/Blinking
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Characteristics of the I2C Bus
        1. 9.5.1.1 Bit Transfer
        2. 9.5.1.2 Start and Stop Conditions
      2. 9.5.2 System Configuration
      3. 9.5.3 Acknowledge
      4. 9.5.4 Device Address
      5. 9.5.5 Regular I2C Bus Slave Address
        1. 9.5.5.1 Regular I2C Bus Slave Address
      6. 9.5.6 LED All Call I2C Bus Address
      7. 9.5.7 LED Sub Call I2C Bus Address
      8. 9.5.8 Software Reset I2C Bus Address
      9. 9.5.9 Control Register
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 Mode Register 1 (MODE1)
        2. 9.6.1.2 Mode Register 2 (MODE2)
        3. 9.6.1.3 Individual Brightness Control Registers (PWM0-PWM7)
        4. 9.6.1.4 Group Duty Cycle Control Register (GRPPWM)
        5. 9.6.1.5 Group Frequency Register (GRPFREQ)
        6. 9.6.1.6 LED Driver Output State Registers (LEDOUT0, LEDOUT1)
        7. 9.6.1.7 I2C Bus Sub-Address Registers 1 to 3 (SUBADR1-SUBADR3)
        8. 9.6.1.8 LED All Call I2C Bus Address Register (ALLCALLADR)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Setting LED Current
      2. 10.1.2 PWM Brightness Dimming
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Community Resources
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

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9 Detailed Description

9.1 Overview

The TLC59208F is an I2C bus controlled 8-bit LED driver optimized for red, green, blue, or amber (RGBA) colormixing applications. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that operates at 97 kHz with a duty cycle adjustable from 0% to 99.6% to allow the LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds with a duty cycle adjustable from 0% to 99.6% that can either dim or blink all LEDs with the same value.

Each LED output can be off, on (no PWM control), set at its individual PWM controller value or at both individual and group PWM controller values. The TLC59208F operates with a supply voltage range of 3 V to 5.5 V and the outputs are 17 V tolerant. LEDs can be directly connected to the TLC59208F device outputs.

Software programmable LED group and three sub call I2C bus addresses allow all or defined groups of TLC59208F devices to respond to a common I2C bus address, allowing for example, all the same color LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C bus commands.

The software reset (SWRST) call allows the master to perform a reset of the TLC59208F through the I2C bus, identical to the power-on reset (POR) that initializes the registers to their default state causing the outputs to be set high (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.

9.2 Functional Block Diagram

TLC59208F fbd_cls715.gif

NOTE:

Only one PWM shown for clarity.

9.3 Feature Description

9.3.1 Power-On Reset

When power is applied to VCC, an internal power-on reset holds the TLC59208F in a reset condition until VCC has reached VPOR. At this point, the reset condition is released and the TLC59208F registers and I2C bus state machine are initialized to their default states causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.2 V to reset the device.

9.3.2 External Reset

A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59208F registers and I2C state machine will be held in their default state until the RESET input is once again high.

This input requires a pull-up resistor to VCC if no active connection is used.

9.3.3 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I2C bus to be reset to the power-up state value through a specific I2C bus command. To be performed correctly, the I2C bus must be functional and there must be no device hanging the bus.

The SWRST Call function is defined as the following:

  1. A Start command is sent by the I2C bus master.
  2. The reserved SWRST I2C bus address 1001 111 with the R/W bit set to 0 (write) is sent by the I2C bus master.
  3. The TLC59208F device(s) acknowledge(s) after seeing the SWRST Call address 1001 0110 (9Eh) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C bus master.
  4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two specific values (SWRST data byte 1 and byte 2):
    1. Byte1 = A5h: the TLC59208F acknowledges this value only. If byte 1 is not equal to A5h, the TLC59208F does not acknowledge it.
    2. Byte 2 = 5Ah: the TLC59208F acknowledges this value only. If byte 2 is not equal to 5Ah, the TLC59208F does not acknowledge it.
  5. If more than two bytes of data are sent, the TLC59208F does not acknowledge any more.

  6. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59208F then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (tBUF).

The I2C bus master may interpret a non-acknowledge from the TLC59208F (at any time) as a SWRST Call Abort. The TLC59208F does not initiate a reset of its registers. This happens only when the format of the Start Call sequence is not correct.

9.3.4 Individual Brightness Control With Group Dimming/Blinking

A 97-kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs):

  • A lower 190-Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control.
  • A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) is used to provide a global blinking control.

TLC59208F brightnessgrpdimsig_cls715.gif
A. Minimum pulse width for LEDn brightness control is 40 ns.
B. Minimum pulse width for group dimming is 20.48 μs.
C. When M = 1 (GRPPWM register value), the resulting LEDn brightness control and group dimming signal will have two pulses of the LED brightness control signal (pulse width = N × 40 ns,w ith N defined in the PWMx register).
D. The resulting brightness plus group dimming signal shown above demonstrate a resulting control signal with M = 4 (8 pulses).
Figure 7. Brightness + Group Dimming Signals

9.4 Device Functional Modes

    Active Active mode occurs when one or more of the output channels is enabled.
    Standby Standby mode occurs when all output channels are disabled. Standby mode may be entered either through I2C command or by pulling the RESET pin low.

9.5 Programming

9.5.1 Characteristics of the I2C Bus

The I2C bus is for two-way two-line communication between different devices or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

9.5.1.1 Bit Transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8).

TLC59208F bit_trans_cls715.gif Figure 8. Bit Transfer

9.5.1.2 Start and Stop Conditions

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is defined as the Stop condition (P) (see Figure 9).

TLC59208F start_stop_cls715.gif Figure 9. Start and Stop Conditions

9.5.2 System Configuration

A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 10).

TLC59208F sys_config_cls715.gif Figure 10. System Configuration

9.5.3 Acknowledge

The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable the master to generate a Stop condition.

TLC59208F ack_nack_cls715.gif Figure 11. Acknowledge on I2C Bus
TLC59208F write_onereg_cls715.gif Figure 12. Write to a Specific Register
TLC59208F wallautoincr2_cls715.gif Figure 13. Write to All Registers Using Auto-Increment
TLC59208F multwrites_cls715.gif Figure 14. Multiple Writes to Individual Brightness Registers Only Using the Auto-Increment Feature
TLC59208F allreads_cls715.gif Figure 15. Read All Registers With the Auto-Increment Feature
TLC59208F ledallcall_cls715.gif
A. In this example, several TLC59208Fs are used with the same sequence sent to each.
B. ALLCALL bit in MODE1 register is equal to 1 for this example.
C. OCH bit in MODE2 register is equal to 1 for this example.
Figure 16. LED All-Call I2C Bus Address Programming and LED All-Call Sequence Example

9.5.4 Device Address

Following a Start condition, the bus master must output the address of the slave it is accessing.

9.5.5 Regular I2C Bus Slave Address

The I2C bus slave address of the TLC59208F is shown in Figure 17. Slave address pins A0, A1, and A2 choose 1 of 64 slave addresses. To conserve power, no internal pullup resistors are incorporated on A0, A1, or A2. Address values, depending on A0, A1, and A2, can be found in Table 1.

NOTE

When using the TLC59208F, reserved I2C bus addresses must be used with caution since they can interfere with the following:

  • Reserved for future use I2C bus addresses (0000 011, 1111 101, 1111 110, 1111 111)
  • Slave devices that use the 10-bit addressing scheme (1111 0xx)
  • High-speed mode master code (0000 1xx)

TLC59208F slave_addr_cls715.gif Figure 17. Slave Address

The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is selected. When set to logic 0, a write operation is selected.

9.5.5.1 Regular I2C Bus Slave Address

Table 1. TLC59208F Address Map

ADDRESS INPUT SLAVE ADDRESS
A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 ADDRESS
GND SCL GND 0 0 1 0 0 0 0 20h
GND SCL VCC 0 0 1 0 0 0 1 22h
GND SDA GND 0 0 1 0 0 1 0 24h
GND SDA VCC 0 0 1 0 0 1 1 26h
VCC SCL GND 0 0 1 0 1 0 0 28h
VCC SCL VCC 0 0 1 0 1 0 1 2Ah
VCC SDA GND 0 0 1 0 1 1 0 2Ch
VCC SDA VCC 0 0 1 0 1 1 1 2Eh
GND SCL SCL 0 0 1 1 0 0 0 30h
GND SCL SDA 0 0 1 1 0 0 1 32h
GND SDA SCL 0 0 1 1 0 1 0 34h
GND SDA SDA 0 0 1 1 0 1 1 36h
VCC SCL SCL 0 0 1 1 1 0 0 38h
VCC SCL SDA 0 0 1 1 1 0 1 3Ah
VCC SDA SCL 0 0 1 1 1 1 0 3Ch
VCC SDA SDA 0 0 1 1 1 1 1 3Eh
GND GND GND 0 1 0 0 0 0 0 40h
GND GND VCC 0 1 0 0 0 0 1 42h
GND VCC GND 0 1 0 0 0 1 0 44h
GND VCC VCC 0 1 0 0 0 1 1 46h
VCC GND GND 0 1 0 0 1 0 0 48h
VCC GND VCC 0 1 0 0 1 0 1 4Ah
VCC VCC GND 0 1 0 0 1 1 0 4Ch
VCC VCC VCC 0 1 0 0 1 1 1 4Eh
GND GND SCL 0 1 0 1 0 0 0 50h
GND GND SDA 0 1 0 1 0 0 1 52h
GND VCC SCL 0 1 0 1 0 1 0 54h
GND VCC SDA 0 1 0 1 0 1 1 56h
VCC GND SCL 0 1 0 1 1 0 0 58h
VCC GND SDA 0 1 0 1 1 0 1 5Ah
VCC VCC SCL 0 1 0 1 1 1 0 5Ch
VCC VCC SDA 0 1 0 1 1 1 1 5Eh
SCL SCL GND 1 0 1 0 0 0 0 A0h
SCL SCL VCC 1 0 1 0 0 0 1 A2h
SCL SDA GND 1 0 1 0 0 1 0 A4h
SCL SDA VCC 1 0 1 0 0 1 1 A6h
SDA SCL GND 1 0 1 0 1 0 0 A8h
SDA SCL VCC 1 0 1 0 1 0 1 AAh
SDA SDA GND 1 0 1 0 1 1 0 ACh
SDA SDA VCC 1 0 1 0 1 1 1 AEh
SCL SCL SCL 1 0 1 1 0 0 0 B0h
SCL SCL SDA 1 0 1 1 0 0 1 B2h
SCL SDA SCL 1 0 1 1 0 1 0 B4h
SCL SDA SDA 1 0 1 1 0 1 1 B6h
SDA SCL SCL 1 0 1 1 1 0 0 B8h
SDA SCL SDA 1 0 1 1 1 0 1 BAh
SDA SDA SCL 1 0 1 1 1 1 0 BCh
SDA SDA SDA 1 0 1 1 1 1 1 BEh
SCL GND GND 1 1 0 0 0 0 0 C0h
SCL GND VCC 1 1 0 0 0 0 1 C2h
SCL VCC GND 1 1 0 0 0 1 0 C4h
SCL VCC VCC 1 1 0 0 0 1 1 C6h
SDA GND GND 1 1 0 0 1 0 0 C8h
SDA GND VCC 1 1 0 0 1 0 1 CAh
SDA VCC GND 1 1 0 0 1 1 0 CCh
SDA VCC VCC 1 1 0 0 1 1 1 CEh
SCL GND SCL 1 1 1 0 0 0 0 E0h
SCL GND SDA 1 1 1 0 0 0 1 E2h
SCL VCC SCL 1 1 1 0 0 1 0 E4h
SCL VCC SDA 1 1 1 0 0 1 1 E6h
SDA GND SCL 1 1 1 0 1 0 0 E8h
SDA GND SDA 1 1 1 0 1 0 1 EAh
SDA VCC SCL 1 1 1 0 1 1 0 ECh
SDA VCC SDA 1 1 1 0 1 1 1 EEh

9.5.6 LED All Call I2C Bus Address

  • Default power-up value (ALLCALLADR address register): 90h or 1001 000
  • Programmable through I2C bus (volatile programming)
  • At power-up, LED All Call I2C bus address is enabled. TLC59208F sends an ACK when 90h (R/W = 0) or 91h (R/W = 1) is sent by the master.

NOTE

The default LED All Call I2C bus address (90h or 1001 000) must not be used as a regular I2C bus slave address since this address is enabled at power-up. All the TLC59208Fs on the I2C bus will acknowledge the address if sent by the I2C bus master.

9.5.7 LED Sub Call I2C Bus Address

  • Three different I2C bus addresses can be used
  • Default power-up values:
    • SUBADR1 register: 92h or 1001 001
    • SUBADR2 register: 94h or 1001 010
    • SUBADR3 register: 98h or 1001 100
  • Programmable through I2C bus (volatile programming)
  • At power-up, Sub Call I2C bus address is disabled. TLC59208F does not send an ACK when 92h (R/W = 0) or 93h (R/W = 1) or 94h (R/W = 0) or 95h (R/W = 1) or 98h (R/W = 0) or 99h (R/W = 1) is sent by the master.

NOTE

The default LED Sub Call I2C bus address may be used as a regular I2C bus slave address as long as the SUBADRx bits are disabled.

9.5.8 Software Reset I2C Bus Address

The address shown in Figure 18 is used when a reset of the TLC59208F needs to be performed by the master. The software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59208F does not acknowledge the SWRST. See Software Reset for more detail.

TLC59208F sw_rst_addr_cls715.gif Figure 18. Software Reset Address

NOTE

The Software Reset I2C bus address is a reserved address and cannot be use as a regular I2C bus slave address or as an LED All Call or LED Sub Call address.

9.5.9 Control Register

Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the TLC59208F, which will be stored in the Control register. The lowest 5 bits are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options (AI[2:0]).

TLC59208F control_reg_cls715.gif Figure 19. Control Register

When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values.

Table 2. Auto-Increment Options(1)

AI2 AI1 AI0 DESCRIPTION
0 0 0 No auto-increment
1 0 0 Auto-increment for all registers. D[4:0] roll over to '0 0000' after the last register ('1 0001') is accessed.
1 0 1 Auto-increment for individual brightness registers only. D[4:0] roll over to '0 0010' after the last register ('0 1001') is accessed.
1 1 0 Auto-increment for global control registers only. D[4:0] roll over to '0 1010' after the last register ('0 1011') is accessed.
1 1 1 Auto-increment for individual and global control registers only. D[4:0] roll over to '0 0010' after the last register ('0 1011') is accessed.
(1) Other combinations not shown in Table 2 (A1[2:0] = 001, 010, and 011) are reserved and must not be used for proper device operation.

AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I2C bus communication, for example, changing color setting to another color setting.

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I2C bus communication, for example, global brightness or blinking change.

AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C bus communication, for example, changing color and global brightness at the same time.

Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.

When Control register is written, the register entry point determined by D[4:0] is the first register that will be addressed (read or write operation), and can be anywhere between 0 0000 and 1 0001 (as defined in LINKTOTABLE3). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See for rollover values. For example, if the Control register = 1110 1100 (ECh), then the register addressing sequence will be (in hex):

04 →… → 11 → 02 →… → 11 → 02 →… → 11 as long as the master keeps sending or reading data.

9.6 Register Maps

9.6.1 Register Descriptions

Table 3 describes the registers in the TLC59208F.

Table 3. Register Descriptions

REGISTER NUMBER
(HEX)
NAME ACCESS(1) DESCRIPTION
00 MODE1 R/W Mode register 1
01 MODE2 R/W Mode register 2
02 PWM0 R/W Brightness control LED0
03 PWM1 R/W Brightness control LED1
04 PWM2 R/W Brightness control LED2
05 PWM3 R/W Brightness control LED3
06 PWM4 R/W Brightness control LED4
07 PWM5 R/W Brightness control LED5
08 PWM6 R/W Brightness control LED6
09 PWM7 R/W Brightness control LED7
0A GRPPWM R/W Group duty cycle control
0B GRPFREQ R/W Group frequency
0C LEDOUT0 R/W LED output state 0
0D LEDOUT1 R/W LED output state 1
0E SUBADR1 R/W I2C bus sub-address 1
0F SUBADR2 R/W I2C bus sub-address 2
10 SUBADR3 R/W I2C bus sub-address 3
11 ALLCALLADR R/W LED all call I2C bus address
(1) R = read, W = write

9.6.1.1 Mode Register 1 (MODE1)

Table 4 describes Mode Register 1.

Table 4. MODE1 – Mode Register 1 (Address 00h) Bit Description

BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
7 AI2 R 0(1) Register auto-increment disabled
1 Register auto-increment enabled
6 AI1 R 0(1) Auto-increment bit 1 = 0
1 Auto-increment bit 1 = 1
5 AI0 R 0(1) Auto-increment bit 0 = 0
1 Auto-increment bit 0 = 1
4 SLEEP R/W 0 Normal mode(2)
1(1) Low power mode. Oscillator off(3).
3 SUB1 R/W 0(1) Device does not respond to I2C bus sub-address 1.
1 Device responds to I2C bus sub-address 1.
2 SUB2 R/W 0(1) Device does not respond to I2C bus sub-address 2.
1 Device responds to I2C bus sub-address 2.
1 SUB3 R/W 0(1) Device does not respond to I2C bus sub-address 3.
1 Device responds to I2C bus sub-address 3.
0 ALLCALL R/W 0 Device does not respond to LED All Call I2C bus address.
1(1) Device responds to LED All Call I2C bus address.
(1) Default value
(2) It takes 500 μs max. for the oscillator to be up and running once SLEEP bit has been set from logic 1 to 0. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 500 μs window.
(3) No LED control (on, off, blinking, or dimming) is possible when the oscillator is off. Write to a register cannot be accepted during SLEEP mode. When you change the LED condition, SLEEP bit must be set to logic 0.

9.6.1.2 Mode Register 2 (MODE2)

Table 5 describes Mode Register 2.

Table 5. MODE2 – Mode Register 2 (Address 01h) Bit Description

BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
7:6 R 00(1) Reserved
5 DMBLNK R/W 0(1) Group control = dimming
1 Group control = blinking
4 R 0(1) Reserved
3 OCH R/W 0(1) Outputs change on Stop command(2).
1 Outputs change on ACK.
2 WDT ENABLE R/W 0(1) Disable WDT
1 Enable WDT
1:0 WDT PERIOD R/W 00 5 ms
01 15 ms
10 25 ms
11(1) 35 ms
(1) Default value
(2) Change of the outputs at the STOP command allows synchronizing outputs of more than one TLC59208F. Applicable to registers from 02h (PWM0) to 0Dh (LEDOUT) only.

9.6.1.3 Individual Brightness Control Registers (PWM0–PWM7)

Table 6 describes the Individual Brightness Control Registers.

Table 6. PWM0–PWM7 – Individual Brightness Control Registers (Addresses 02h–09h) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000(1) PWM0 individual duty cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000(1) PWM1 individual duty cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000(1) PWM2 individual duty cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000(1) PWM3 individual duty cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000(1) PWM4 individual duty cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000(1) PWM5 individual duty cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000(1) PWM6 individual duty cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000(1) PWM7 individual duty cycle
(1) Default value

A 97-kHz fixed-frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).

duty cycle = TLC59208F ineq1_cls715.gif

9.6.1.4 Group Duty Cycle Control Register (GRPPWM)

Table 7 describes the Group Duty Cycle Control Register .

Table 7. GRPPWM – Group Duty Cycle Control Register (Address 0Ah) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
0Ah GRPPWM 7:0 GDC0[7:0] R/W 1111 1111(1) GRPPWM register
(1) Default value

When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed frequency signal is superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.

General brightness for the 8 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

duty cycle = TLC59208F ineq2_cls715.gif

9.6.1.5 Group Frequency Register (GRPFREQ)

Table 7 describes the Group Frequency Register.

Table 8. GRPFREQ – Group Frequency Register (Address 0Bh) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
0Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000(1) GRPFREQ register
(1) Default value

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0. Applicable to LED output programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).

globalblinkingperiod = TLC59208F ineq3_cls715.gif

9.6.1.6 LED Driver Output State Registers (LEDOUT0, LEDOUT1)

Table 9 describes the LED Driver Output State Registers.

Table 9. LEDOUT0 and LEDOUT1 – LED Driver Output State Registers (Address 0Ch and 0Dh) Bit Descriptions

ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
0Ch LEDOUT0 7:6 LDR3[1:0] R/W 00(1) LED3 output state control
5:4 LDR2[1:0] 00(1) LED2 output state control
3:2 LDR1[1:0] 00(1) LED1 output state control
1:0 LDR0[1:0] 00(1) LED0 output state control
0Dh LEDOUT1 7:6 LDR7[1:0] R/W 00(1) LED7 output state control
5:4 LDR6[1:0] 00(1) LED6 output state control
3:2 LDR4[1:0] 00(1) LED5 output state control
1:0 LDR4[1:0] 00(1) LED4 output state control
(1) Default value

LDRx = 00 : LED driver x is off (default power-up state).

LDRx = 01 : LED driver x is fully on (individual brightness and group dimming/blinking not controlled).

LDRx = 10 : LED driver x is individual brightness can be controlled through its PWMx register.

LDRx = 11 : LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.

9.6.1.7 I2C Bus Sub-Address Registers 1 to 3 (SUBADR1–SUBADR3)

Table 10 describes the Output Gain Control Register.

Table 10. SUBADR1–SUBADR3 – I2C Bus Sub-Address Registers 1 to 3 (Addresses 0Eh–10h) Bit Descriptions

ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
0Eh SUBADR1 7:1 A1[7:1] R/W 1001 001(1) I2C bus sub-address 1
0 A1[0] R 0(1) Reserved
0Fh SUBADR2 7:1 A2[7:1] R/W 1001 010(1) I2C bus sub-address 2
0 A2[0] R 0(1) Reserved
10h SUBADR3 7:1 A3[7:1] R/W 1001 100(1) I2C bus sub-address 3
0 A3[0] R 0(1) Reserved
(1) Default value

Sub-addresses are programmable through the I2C bus. Default power-up values are 92h, 94h, 98h and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0).

Once sub-addresses have been programmed to their right values, SUBx bits need to be set to 1 in order to have the device acknowledging these addresses (MODE1 register).

Only the 7 MSBs representing the I2C bus sub-address are valid. The LSB in SUBADRx register is a read-only bit (0).

When SUBx is set to 1, the corresponding I2C bus sub-address can be used during either an I2C bus read or write sequence.

9.6.1.8 LED All Call I2C Bus Address Register (ALLCALLADR)

Table 11 describes the LED All Call I2C Bus Address Register.

Table 11. ALLCALLADR – LED All Call I2C Bus Address Register Addresses 11h) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS(1) VALUE DESCRIPTION
11h ALLCALLADR 7:1 AC[7:1] R/W 1101 000(1) ALLCALL I2C bus address
0 AC[0] R 0(1) Reserved
(1) Default value

The LED All Call I2C bus address allows all the TLC59208Fs in the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default state)). This address is programmable through the I2C-bus and can be used during either an I2C bus read or write sequence. The register address can also be programmed as a Sub Call.

Only the 7 MSBs representing the All Call I2C bus address are valid. The LSB in ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.