SLVSA51E March   2010  – September 2016 TLC5940-EP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Parameter Equations
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interface
      2. 8.3.2 Error Information Output
      3. 8.3.3 TEF: Thermal Error Flag
      4. 8.3.4 LOD: LED Open Detection
      5. 8.3.5 Delay Between Outputs
      6. 8.3.6 Output Enable
      7. 8.3.7 Setting Maximum Channel Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes
      2. 8.4.2 Setting Dot Correction
      3. 8.4.3 Setting Grayscale
      4. 8.4.4 Status Information Output
      5. 8.4.5 Grayscale PWM Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1 Serial Data Transfer Rate
        2. 9.2.2.2 Grayscale (GS) Data
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation Calculation
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

  1. Place the decoupling capacitor near the VCC pin and GND plane.
  2. Place the current programming resistor Riref close to IREF pin and IREFGND pin.
  3. Route the GND pattern as widely as possible for large GND currents.
  4. Routing wire between the LED cathode side and the device OUTn pin should be as short and straight as possible to reduce wire inductance.
  5. When several ICs are chained, symmetric placements are recommended.

11.2 Layout Example

TLC5940-EP layout_slvs515.gif Figure 25. Layout Recommendation

11.3 Power Dissipation Calculation

The device power dissipation must be below the power dissipation rating of the device package to ensure correct operation. Equation 11 calculates the power dissipation of device:

Equation 11. TLC5940-EP q_pd_lvs515.gif

where

  • VCC: device supply voltage
  • ICC: device supply current
  • VOUT: TLC5940-EP OUTn voltage when driving LED current
  • IMAX: LED current adjusted by R(IREF) Resistor
  • DCn: maximum dot correction value for OUTn
  • N: number of OUTn driving LED at the same time
  • dPWM: duty cycle defined by BLANK pin or GS PWM value