SBVS127E March   2009  – July 2017 TLC5951

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Pin Equivalent Input and Output Schematic Diagrams
    2. 8.2 Test Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Thermal-Shutdown and Thermal-Error Flags
      2. 9.3.2 Noise Reduction
    4. 9.4 Device Functional Modes
      1. 9.4.1 Maximum Constant Sink-Current Value
      2. 9.4.2 Dot Correction (DC) Function
      3. 9.4.3 Global Brightness Control (BC) Function
      4. 9.4.4 Grayscale (GS) Function (PWM Control)
        1. 9.4.4.1 PWM Counter 12-Bit Mode Without Auto Repeat
        2. 9.4.4.2 PWM Counter 8-, 10-, or 12-Bit Mode Without Auto Repeat
        3. 9.4.4.3 PWM Counter 8-, 10-, or 12-Bit Mode With Auto Repeat
      5. 9.4.5 Register and Data Latch Configuration
        1. 9.4.5.1 288-Bit Common Shift Register
        2. 9.4.5.2 Grayscale Data Latch
        3. 9.4.5.3 DC, BC, FC, and UD Shift Register
          1. 9.4.5.3.1 DC, BC, FC, and UD Data Latch
          2. 9.4.5.3.2 Dot-Correction Data Latch
          3. 9.4.5.3.3 Global-Brightness Control-Data Latch
          4. 9.4.5.3.4 Function-Control Data Latch
          5. 9.4.5.3.5 User-Defined Data Latch
      6. 9.4.6 Status Information Data (SID)
      7. 9.4.7 Continuous Base LOD, LSD, and TEF
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

DAP PowerPAD Package
38-Pin HTSSOP With Exposed Thermal Pad
(Top View)
RHA and RTA Packages
40-Pin VQFN and WQFN With Exposed Thermal Pads
(Top View)

NOINDENT:

NC = no internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
DAP RHA, RTA
DCSCK 37 24 I Serial-data shift clock for the 216-bit DC, BC, FC, and UD shift register. Data present on DCSIN are shifted into the LSB of the shift register with the DCSCK rising edge. Data in the shift register are shifted toward the MSB at each DCSCK rising edge. The MSB data of the register appear on DCSOUT. The 216-bit data in the shift register are automatically copied to the DC, BC, FC, and UD data latch 3 ms to 7 ms following the last rising edge after DCSCK stops switching.
DCSIN 38 25 I Serial data input for the 216-bit DC, BC, FC, and UD shift register. DCSIN is connected to the LSB of the shift register.
DCSOUT 20 6 O Serial data output of the 216-bit shift register. DCSOUT is connected to the MSB of the shift register. Data are clocked out at the rising edge of DCSCK.
GND 33 20 — Power ground
GSCKB 6 31 I Reference clock for the GS PWM control for the BLUE LED output group. When XBLNK is high, each GSCKR rising edge increments the BLUE LED GS counter for PWM control.
GSCKG 4 29 I Reference clock for the GS PWM control for the GREEN LED output group. When XBLNK is high, each GSCKR rising edge increments the GREEN LED GS counter for PWM control.
GSCKR 5 30 I Reference clock for the GS pulse-width modulation (PWM) control for the RED LED output group. When XBLNK is high, each GSCKR rising edge increments the RED LED GS counter for PWM control.
GSLAT 3 28 I Data in the 288-bit common shift register are copied to the GS data latch or to the DC, BC, and FC data latch at the rising edge of GSLAT. The level of GSLAT at the last GSSCK before the GSLAT rising edge determines which of the two latches the data are transferred into. When GSLAT is low at the last GSSCK rising edge, all 288 bits in the common shift register are copied to the GS data latch. When GSLAT is high at the last GSSCK rising edge, bits 0–198 are copied to the DC, BC, and FC data latch and bits 199–215 are copied to the 216-bit DC, BC, FC, and UD shift register. The GSLAT rising edge for a DC, BC, FC, and UD data write must be input more than 7 ms after a data write through the DCSIN pin.
GSSCK 2 27 I Serial data shift clock for the 288-bit common shift register for GS, DC, BC, and FC data. Data present on GSSIN are shifted into the LSB of the shift register with the rising edge of GSSCK. Data in the shift register are shifted toward the MSB at each rising edge of GSSCK. The MSB data of the shift register appear on GSSOUT.
GSSIN 1 26 I Serial data input for the 288-bit common shift register for grayscale (GS), dot correction (DC), global brightness control (BC), and function control (FC) data. GSSIN is connected to the LSB of the 288-bit common shift register. This pin is internally pulled to GND with a 500-kΩ resistor.
GSSOUT 19 5 O Serial data output of the 288-bit common shift register. LED-open detection (LOD), LED-short detection (LSD), thermal error flag (TEF), and 199-bit data in the DC, BC, and FC data latch can be read via GSSOUT. GSSOUT is connected to the MSB of the shift register. Data are clocked out at the rising edge of GSSCK.
IREF 34 21 I/O A resistor connected between IREF and GND sets the maximum current for all constant-current outputs.
NC — 4, 7 — No internal connection
OUTB0–
OUTB7		 9, 12, 15, 18, 21, 24, 27, 30 34, 37, 40, 3, 8, 11, 14, 17 O Constant-current outputs for the BLUE LED group. These outputs are controlled with the GSCKB clock signal.
The BLUE LED group is divided into four subgroups: OUTB0 and OUTB4, OUTB1and OUTB5, OUTB2 and OUTB6, and OUTB3 and OUTB7.
Each paired output turns on or off with 24 ns (typ) time delay between other paired outputs. Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be applied to each output.
OUTG0–
OUTG7		 7, 10, 13, 16, 23, 26, 29, 32 32, 35, 38, 1, 10, 13, 16, 19 O Constant-current outputs for the GREEN LED group. These outputs are controlled with the GSCKG clock signal.
The GREEN LED group is divided into four subgroups: OUTG0 and OUTG4, OUTG1 and OUTG5, OUTG2 and OUTG6, and OUTG3 and OUTG7.
Each paired output turns on or off with 24 ns (typ) time delay between other paired outputs. Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be applied to each output.
OUTR0–
OUTR7		 8, 11, 14, 17, 22, 25, 28, 31 33, 36, 39, 2, 9, 12, 15, 18 O Constant-current outputs for the RED LED group. These outputs are controlled with the GSCKR clock signal.
The RED LED group is divided into four subgroups: OUTR0 and OUTR4, OUTR1 and OUTR5, OUTR2 and OUTR6, and OUTR3 and OUTR7.
Each paired output turns on or off with 24 ns (typ) time delay between other paired outputs. Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be applied to each output.
VCC 35 22 — Power supply
XBLNK 36 23 I When XBLNK is low, all constant-current outputs (OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7) are forced off. The grayscale counters for each color group are reset to 0, and the grayscale PWM timing controller is initialized. When XBLNK is high, all constant-current outputs are controlled by the grayscale PWM timing controller for each color LED. This pin is internally pulled to GND with a 500-kΩ resistor.