JAJSFT9A May   2009  – July 2018 TLC5952

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路 (複数のTLC5952のデイジー・チェーン接続)
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Pin Equivalent Input and Output Schematic Diagrams
    2. 7.2 Test Circuits
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Maximum Constant-Sink-Current Value
      2. 8.3.2 Global Brightness Control (BC) Function: Sink-Current Control
      3. 8.3.3 Constant-Current Output On-Off Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 LOD, LSD, and TEF Operation
      2. 8.4.2 Register and Data Latch Configuration
        1. 8.4.2.1 Output On-Off Data Latch
        2. 8.4.2.2 Control-Data Latch
        3. 8.4.2.3 Status Information Data (SID)
        4. 8.4.2.4 LED-Open Detection (LOD), LED-Short Detection (LSD), And Thermal Error Flag (TEF)
        5. 8.4.2.5 Thermal Shutdown (TSD)
        6. 8.4.2.6 Noise Reduction
  9. 9 Power Supply Recommendations
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 コミュニティ・リソース
    3. 10.3 商標
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DAP PowerPAD™ Package
32-Pin HTSSOP With Exposed Thermal Pad
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BLANK 29 I All outputs are blank. When BLANK is high, all constant-current outputs (OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7) are forced off. When BLANK is low, all constant current outputs are controlled by the on-off control data in the data latch.
GND 1 — Power ground
IREF 32 I/O Reference current terminal. The maximum current for the outputs OUTR0–OUTR7, OUTG0–OUTG7, and OUTB0–OUTB7 is set with a resistor from IREF to GND.
LAT 4 I Edge-triggered latch. The rising edge of LAT latches the data from the common shift register into the output on-off data latch. See the Output On-Off Data Latchsection for more details.
OUTB0–OUTB7 7, 10, 13, 16, 19, 22, 25, 28 O Constant-current outputs for the BLUE LED group.
Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on-off control data latch.
OUTG0–OUTG7 6, 9, 12, 15, 18, 21, 24, 27 O Constant-current outputs for the GREEN LED group.
Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on-off control data latch.
OUTR0–OUTR7 5, 8, 11, 14, 17, 20, 23, 26 O Constant-current outputs for the RED LED group.
Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on-off control data latch.
SCLK 3 I Serial data shift clock. Data present on SIN are shifted to the LSB of the common shift register with the rising edge of SCLK. Data in the shift register are shifted toward the MSB at each rising edge of SCLK. The MSB data of the common shift register appear on SOUT.
SIN 2 I Serial data input for the 25-bit common shift register
SOUT 30 O Serial data output. The MSB of the 25-bit common shift register is shifted out at the rising edge of SCLK.
VCC 31 — Power-supply voltage