The TLC5957 is a 48-channel constant current sink driver. Each channel has an individually-adjustable, 65536-step, pulse width modulation (PWM) grayscale (GS) brightness control.
The output channels are divided into three groups, each group has a 512 step color brightness control (CC), CC adjusts brightness between colors. The maximum current value of all 48 channels can be set by 8-step global brightness control (BC). BC adjusts brightness deviation between LED drivers. GS, CC and BC data are accessible via a serial interface port.
TLC5957 has one error flag: LED open detection (LOD), which can be read via a serial interface port. Each constant-current has a pre-charge field- effect transistor (FET), which can remove ghosting and improve display performance on the multiplexing LED display. Besides, TLC5957 has an enhanced circuit, it can cancel the caterpillar effect caused by LED open.
TLC5957 has a poker data transmission mode; GS data length can be configured from 9 bit to 16 bit according to PWM bits in each sub-segment. Poker Mode can significantly increase visual refresh rate in multiplexing applications.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
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TLC5957 | QFN (56) | 8.0 mm × 8.0 mm |
DATE | REVISION | NOTES |
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October 2014 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
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NAME | NO. | ||
GCLK | 29 | I | Grayscale(GS) pulse width modulation (PWM) reference clock control for OUTXn. |
Each GCLK rising edge increase the GS counter by1 for PWM control. | |||
GND | ThermalPad | — | Power ground. The thermal pad must be soldered to GND on PCB. |
IREF | 1 | — | Maximum constant-current value setting. The OUTR0 to OUTB15 maximum constant output current are set to the desired values by connecting an external resistor between IREF and IREFGND. See Equation 1 for more detail. The external resistor should be placed close to the device. |
IREFGND | 56 | — | Analog ground. Dedicated ground pin for the external IREF resistor. This pin should be connected to analog ground trace which is connected to power ground near the common GND point of board. |
LAT | 27 | I | The LAT falling edge latches the data from the common shift register into the GS data latch or FC data latch. |
OUTR0-R15 | 8, 11, 14, 17, 20, 23, 30, 33, 36, 39, 44, 47, 50, 53, 2, 5 | O | Constant current output for RED LED. Multiple outputs can be tied together to increase the constant current capability. Different voltages can be applied to each output. These outputs are turned on-off by GCLK signal and the data in GS data memory. |
OUTG0-G15 | 9, 12, 15, 18, 21, 24, 31, 34, 37, 40, 45, 48, 51, 54, 3, 6 | O | Constant current output for GREEN LED. Multiple outputs can be tied together to increase the constant current capability. Different voltages can be applied to each output. These outputs are turned on-off by GCLK signal and the data in GS data memory. |
OUTB0-B15 | 10, 13, 16, 19, 22, 25, 32, 35, 38, 41, 46, 49, 52, 55, 4, 7 | O | Constant current output for BLUE LED. Multiple outputs can be tied together to increase the constant current capability. Different voltages can be applied to each output. These outputs are turned on-off by GCLK signal and the data in GS data memory. |
SCLK | 28 | I | Serial data shift clock. Data present on SIN are shifted to the 48-bit common shift register LSB with the SCLK rising edge. Data in the shift register are shifted towards the MSB at each SCLK rising edge. The common shift register MSB appears on SOUT. |
SIN | 26 | I | Serial data input of the 48-bit common shift register. When SIN is high level, the LSB is set to '1' for only one SCLK input rising edge. If two SCLK rising edges are input while SIN is high, then the 48-bit shift register LSB and LSB+1 are set to '1'. When SIN is low, the LSB is set to '0' at the SCLK input rising edge. |
SOUT | 42 | O | Serial data output of the 48-bit common shift register. SOUT is connected to the MSB of the register. |
VCC | 43 | — | Power-supply voltage. |