SBVS146D August   2010  – December 2015 TLC5971

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. 7 Parametric Measurement Information
    1. 7.1 Test Circuits
    2. 7.2 Pin Equivalent Input and Output Schematics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Auto Display Repeat Function
      2. 8.3.2 Display Timing Reset Function
      3. 8.3.3 Output Timing Select Function
      4. 8.3.4 Thermal Shutdown
      5. 8.3.5 Noise Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Maximum Constant Sink Current Setting
    5. 8.5 Programming
      1. 8.5.1 Global Brightness Control (BC) Function (Sink Current Control)
      2. 8.5.2 Grayscale (GS) Function (PWM Control)
      3. 8.5.3 Enhanced Spectrum (ES) PWM Control
      4. 8.5.4 Register and Data Latch Configuration
        1. 8.5.4.1 224-Bit Shift Register
        2. 8.5.4.2 218-Bit Data Latch
      5. 8.5.5 Internal Latch Pulse Generation Timing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Define Basic Parameters
        2. 9.2.2.2 Data Input Sequence
        3. 9.2.2.3 How to Control the TLC5971
          1. 9.2.2.3.1 Data Write and PWM Control with Internal Grayscale Clock Mode
          2. 9.2.2.3.2 Data Write and PWM Control with External Grayscale Clock Mode
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The device is a 12-channel, constant sink current, LED driver. This device can be connected in series to drive many LED lamps with only a few controller ports. Functional control data and PWM control data can be written from the SDI and SCK input terminal. The PWM timing reference clock can be chosen from the internal oscillation or external SCK signal.

9.2 Typical Application

TLC5971 typ_app_ex1_bvs146.gif
The output voltage range is from 0 V to 3.3 V.
NOTE: The number of LEDs in series changes, depending on the VCC voltage.
Figure 31. Typical Application Circuit Example (Internal Linear Regulator Using VCC = 6 V to 17 V)

9.2.1 Design Requirements

For this design example, use Table 6 as the input parameters.

Table 6. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VCC Input Voltage Range 3 V to 5.5 V
LED Lamp (VLED) Input Voltage Range Maximum 17 V
SIN, SCLK, LAT and GSCLK Voltage Range Low Level = GND, High Level = VCC

9.2.2 Detailed Design Procedure

9.2.2.1 Define Basic Parameters

To begin the design process, a few parameters must be decided as following"

  • Maximum output constant-current value for each color LED lamp
  • Maximum LED forward voltage (Vf) and maximum VLED
  • Total LEDs and Cascaded IC Number

9.2.2.2 Data Input Sequence

224-bit data packets are sent through single-wire interface for the PWM control of three output channels. Select the BC data, FC data and write the GS data to the register following the signal timing.

9.2.2.3 How to Control the TLC5971

To set each function mode, BC color, GS output, 6-bit write command, 5-bit FC data, 21-bit BC data for each color group, and 192-bit GS data for OUTXn, a total number of 224 bits must be written into the device. Figure 32 shows the 224-bit data packet configuration.

When N units of the TLC5971 are cascaded (as shown in Figure 33), N × 224 bits must be written from the controller into the first device to control all devices. The number of cascaded devices is not limited as long as the proper voltage is supplied to the device at VCC. The packets for all devices must be written again whenever the data in one packet is changed.

TLC5971 ai_config_224data_bvs146.gif Figure 32. 224-Bit Data Packet Configuration
TLC5971 ai_cascase_conex_bvs146.gif Figure 33. Cascading Connection of N TLC5971 Units

9.2.2.3.1 Data Write and PWM Control with Internal Grayscale Clock Mode

When the EXTCLK bit is 0, the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for illumination applications that change the display image at low frequencies. The data and clock timing is shown in Figure 3 and Figure 34. A writing procedure for the function setting and display control follows:

  1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
  2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC5971 using the SDTI and SCKI signals. The first six bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK bit must be set to 0 for the internal oscillator mode. Also, the DSPRPT bit should be set to 1 to repeat the PWM timing control and BLANK set to 0 to start the PWM control.
  3. Write the 224-bit data packet for the (N – 1) TLC5971 without delay after step 2.
  4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is now 224 × N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.
TLC5971 ai_tim_strt_updt1_bvs146.gif Figure 34. Data Packet and Display Start/Update Timing 1 (Internal Oscillator Mode)

9.2.2.3.2 Data Write and PWM Control with External Grayscale Clock Mode

When the EXTCLK bit is 1, the data shift clock (SCKI) is used for PWM control of OUTXn (X = R/G/B and n = 0-3) as the GS reference clock. This mode is ideal for video image applications that change the display image with high frequencies or for certain display applications that must synchronize all TLC5971s. The data and clock timing are shown in Figure 3 and Figure 35. A writing procedure for the display data and display timing control follows:

  1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
  2. Write the 224-bit data packet MSB-first for the Nth TLC5971 using the SDTI and SCKI signals. The first six bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that the PWM control is not repeated, the TMGRST bit should be set to 1 to reset the PWM control timing at the internal latch pulse generation, and BLANK must be set to 0 to start the PWM control.
  3. Write the 224-bit data for the (N – 1) TLC5971 without delay after step 2.
  4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is 224 × N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
  5. To start the PWM control, send one pulse of the SCKI clock with SDTI low after 1.34 µs or more from step 4. The OUTXn are turned on when the output GS data are not 0000h.
  6. Send the remaining 65535 SCKI clocks with SDTI low. Then the PWM control for OUTXn is synchronized with the SCKI clock and one display period is finished with a total of 65536 SCKI clock periods.
  7. Repeat step 2 to step 6 for the next display period.
TLC5971 ai_tim_strt_updt2_bvs146.gif Figure 35. Data Packet and Display Start/Update Timing 2 (External Clock Mode)

There is another control procedure that is recommended for a long chain of cascaded devices. The data and clock timings are shown in Figure 3 and Figure 36. When 256 TLC5971 units are cascaded, use the following procedure:

  1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
  2. Write the 224-bit data packet MSB-first for the 256th TLC5971 using the SDTI and SCKI signals. The EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that the PWM control does not repeat, the TMGRST bit should be set to 1 to reset the PWM control timing with the internal latch pulse, and BLANK must be set to 0 to start the PWM control.
  3. Repeat the data write sequence for all TLC5971s. The total shift clock count (SCKI) is 57344 (224 × 256). After all device data are written, stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
  4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34 µs or more from step 3 (or step 7). These 8192 clock periods are used for the OUTXn PWM control.
  5. Write the new 224-bit data packets to the 256th to first TLC5971s for the next display with 256 × 224 SCKI clock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock and one display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used for PWM control and, at the same time, to write data into the shift registers of all cascaded parts.
  6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and the second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the 218-bit data latch in all devices.
  7. Repeat step 4 to step 6 for the next display periods.
TLC5971 ai_tim_strt_updt3_bvs146.gif Figure 36. Data Packet and Display Start/Update Timing 3
(External Clock Mode With 256 Cascaded Devices)

9.2.3 Application Curve

TLC5971 tlc5971_3_sbvs146.gif Figure 37. Output Waveform With GS Data Latch Input

9.3 System Examples

TLC5971 typ_app_ex2_bvs146.gif
1. The output operating voltage range is from 0 V to VCC.
Figure 38. Typical Application Circuit Example (Direct Power Supplying VCC = 3 V to 5.5 V)
TLC5971 typ_app_ex3_bvs146.gif
1. The output operating voltage range is from 0 V to VCC.
Figure 39. Typical Application Circuit Example
(Direct Power Supplying VCC = 3 V to 5.5 V, VLED = 15 V)