SBVS146D
August 2010 – December 2015
TLC5971
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Switching Characteristics
6.7
Dissipation Ratings
6.8
Typical Characteristics
7
Parametric Measurement Information
7.1
Test Circuits
7.2
Pin Equivalent Input and Output Schematics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Auto Display Repeat Function
8.3.2
Display Timing Reset Function
8.3.3
Output Timing Select Function
8.3.4
Thermal Shutdown
8.3.5
Noise Reduction
8.4
Device Functional Modes
8.4.1
Maximum Constant Sink Current Setting
8.5
Programming
8.5.1
Global Brightness Control (BC) Function (Sink Current Control)
8.5.2
Grayscale (GS) Function (PWM Control)
8.5.3
Enhanced Spectrum (ES) PWM Control
8.5.4
Register and Data Latch Configuration
8.5.4.1
224-Bit Shift Register
8.5.4.2
218-Bit Data Latch
8.5.5
Internal Latch Pulse Generation Timing
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Define Basic Parameters
9.2.2.2
Data Input Sequence
9.2.2.3
How to Control the TLC5971
9.2.2.3.1
Data Write and PWM Control with Internal Grayscale Clock Mode
9.2.2.3.2
Data Write and PWM Control with External Grayscale Clock Mode
9.2.3
Application Curve
9.3
System Examples
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Community Resources
12.2
Trademarks
12.3
Electrostatic Discharge Caution
12.4
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
PWP|20
MHTS001G
RGE|24
MPQF124G
サーマルパッド・メカニカル・データ
PWP|20
PPTD063U
RGE|24
QFND136Y
発注情報
sbvs146d_oa
sbvs146d_pm
11 Layout
11.1 Layout Guidelines
Place the decoupling capacitor near the VCC pin and GND plane.
Route the GND pattern as widely as possible for large GND currents.
Connecting wire between the chained ICs should be as short as possible to reduce wire inductance.
11.2 Layout Example
Figure 40. Layout Example