JAJSFP3A July   2018  – August 2018 TLC6C5716-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Constant-Sink-Current Setting
      2. 7.3.2 Brightness Control and Dot Correction
      3. 7.3.3 Grayscale Configuration
        1. 7.3.3.1 PWM Auto Repeat
        2. 7.3.3.2 PWM Timing Reset
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  LED Diagnostics
        2. 7.3.4.2  Adjacent-Pin-Short Check
        3. 7.3.4.3  IREF-Short and IREF-Open Detection
        4. 7.3.4.4  Pre-Thermal Warning Flag
        5. 7.3.4.5  Thermal Error Flag
        6. 7.3.4.6  Negate-Bit Toggle
        7. 7.3.4.7  LOD_LSD Self-Test
        8. 7.3.4.8  ERR Pin
        9. 7.3.4.9  ERROR Clear
        10. 7.3.4.10 Global Reset
        11. 7.3.4.11 Slew Rate Control
        12. 7.3.4.12 Channel Group Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up
      2. 7.4.2 Device Initialization
      3. 7.4.3 Fault Mode
      4. 7.4.4 Normal Operation
    5. 7.5 Programming
      1. 7.5.1 Register Write and Read
        1. 7.5.1.1 FC-BC-DC Write
          1. 7.5.1.1.1 FC Data Write
          2. 7.5.1.1.2 BC Data Write
          3. 7.5.1.1.3 DC Data Write
        2. 7.5.1.2 Grayscale Data Write
        3. 7.5.1.3 Special Command Function
          1. 7.5.1.3.1 GS Read
          2. 7.5.1.3.2 FC-BC-DC Read
          3. 7.5.1.3.3 Status Information Data Read
    6. 7.6 Register Maps
      1. 7.6.1 GRAYSCALE Registers
        1. 7.6.1.1 OUTn_GS Register (Offset = 0h)
          1. Table 25. OUTn_GS Register Field Descriptions
      2. 7.6.2 FC-BC-DC Registers
        1. 7.6.2.1 FC-BC-DC Register (Offset = 1h)
          1. Table 28. FC-BC-DC Register Field Descriptions
      3. 7.6.3 SID Registers
        1. 7.6.3.1 SID Register (Offset = 2h)
          1. Table 31. SID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4.1 LED Diagnostics

An LOD-LSD detection circuit compares the output voltage with the LOD threshold and LSD threshold, and Table 1 shows the output results.

Table 1. LOD-LSD Detection

OUTPUT VOLTAGE CONDITION DETECTOR OUTPUT BIT VALUE
LOD LSD
VOUTn < LOD_VOLTAGE 1 0
LOD_VOLTAGE < VOUTn < LSD_VOLTAGE 0 0
VOUTn > LSD_VOLTAGE 0 1

The LOD threshold can be configured by the LOD_VOLTAGE bit in the FC-BC-DC register, Table 12 . The threshold is 0.3 V when LOD_VOLTAGE = 0, and the threshold is 0.5 V when LOD_VOLTAGE = 1.

Table 2. LOD Threshold

LOD_VOLTAGE BIT LOD THRESHOLD
0 (Default) 0.3 V
1 0.5 V

The LSD threshold is configured by the LSD_VOLTAGE bit in the FC-BC-DC register, Table 12. The threshold is VVSENSE – 0.3 V when LSD_VOLTAGE = 0, and the threshold is VVSENSE – 0.7 V when LSD_VOLTAGE = 1.

Table 3. LSD Threshold

LSD_VOLTAGE BIT LSD THRESHOLD
0 (Default) VSENSE – 0.3 V
1 VSENSE – 0.7 V

There are two sets of LOD-LSD registers in the device, one is the LOD1-LSD1 registers, the other is the LOD2-LSD2 registers. Each group of registers consists of 24 bits of LOD data and 24 bits of LSD data, corresponding to the 24 channel outputs. The device updates the LOD1-LSD1 registers at the 9th GCLK rising edge. The device updates the LOD2-LSD2 registers at the Nth GCLK rising edge. N is the maximum GCLK number in a PWM period minus 1, see Table 4.

To detect all kinds of LED faults, the output channel should turn ON at the 9th GCLK rising edge, and turn OFF at the Nth GCLK rising edge.

The device integrates an internal pullup circuit for LED diagnostics, shown in Figure 23. The circuit turns off during the channel on-state, but turns on to charge the output pin during the channel-off state. For an LED-short fault, both LSD1 and LSD2 are 1. For an LED-open fault, both LOD1 and LSD2 are 1. For an output short-to-GND fault, both LOD1 and LOD2 are 1. Table 5 shows the details.

TLC6C5716-Q1 OUTx-Block-slasek2.gifFigure 23. Internal Pullup Circuit

Table 4. LOD-LSD Register Latch Timing

GS COUNTER MODE LOD1-LSD1 LOD2-LSD2
12-bit 9th GCLK rising edge 4095th GCLK rising edge
10-bit 9th GCLK rising edge 1023rd GCLK rising edge
8-bit 9th GCLK rising edge 255th GCLK rising edge

Table 5. LED Status Lookup Table

LED STATUS LOD-LSD RESULT
LOD1-LSD1 Updated at 9th GCLK LOD2-LSD2 Updated at Nth GCLK(1)
LED Ok LOD1 0 LOD2 0
LSD1 0 LSD2 1
LED open LOD1 1 LOD2 0
LSD1 0 LSD2 1
LED short LOD1 0 LOD2 0
LSD1 1 LSD2 1
Output short-to-GND LOD1 1 LOD2 1
LSD1 0 LSD2 0
(1) N = 4095 for 12-bit GS mode, 1023 for 10-bit GS mode, 255 for 8-bit GS mode.

In some cases, users may need to turn off output channels before the 9th GCLK to disable the output channels, or turn on the output channels at the Nth GCLK to get more brightness. LOD_LSD faults are reported as shown in Table 6. Users can ignore the fault according to the GS register setting value.

Table 6. PWM Status Lookup Table

PWM STATUS LOD-LSD Result
LOD1-LSD1 UPDATED AT 9th GCLK LOD2-LSD2 UPDATED AT Nth GCLK (1)
PWM OK LOD1 0 LOD2 0
LSD1 0 LSD2 1
Channel off before 9th GCLK LOD1 0 LOD2 0
LSD1 1 LSD2 1
Channel on at Nth GCLK LOD1 0 LOD2 0
LSD1 0 LSD2 0
(1) N = 4095 for 12-bit GS mode, 1023 for 10-bit GS mode, 255 for 8-bit GS mode

The LOD_LSD status is updated every PWM cycle. Figure 14 is an example of the LOD-LSD register update timing for the 12-bit GS mode.