JAJSFY9A December   2017  – August 2018 TLC6C5724-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Constant-Sink-Current Setting
      2. 7.3.2 Brightness Control and Dot Correction
      3. 7.3.3 Grayscale Configuration
        1. 7.3.3.1 PWM Auto Repeat
        2. 7.3.3.2 PWM Timing Reset
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  LED Diagnostics
        2. 7.3.4.2  Adjacent-Pin-Short Check
        3. 7.3.4.3  IREF Short and IREF Open Detection
        4. 7.3.4.4  Pre-Thermal Warning Flag
        5. 7.3.4.5  Thermal Error Flag
        6. 7.3.4.6  Negate Bit Toggle
        7. 7.3.4.7  LOD_LSD Self-Test
        8. 7.3.4.8  ERR Pin
        9. 7.3.4.9  ERROR Clear
        10. 7.3.4.10 Global Reset
        11. 7.3.4.11 Slew Rate Control
        12. 7.3.4.12 Channel Group Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up
      2. 7.4.2 Device Initialization
      3. 7.4.3 Fault Mode
      4. 7.4.4 Normal Operation
    5. 7.5 Programming
      1. 7.5.1 Register Write and Read
        1. 7.5.1.1 FC-BC-DC Write
          1. 7.5.1.1.1 FC Data Write
          2. 7.5.1.1.2 BC Data Write
          3. 7.5.1.1.3 DC Data Write
        2. 7.5.1.2 Grayscale Data Write
        3. 7.5.1.3 Special Command Function
          1. 7.5.1.3.1 GS Read
          2. 7.5.1.3.2 FC-BC-DC Read
          3. 7.5.1.3.3 Status Information Data Read
    6. 7.6 Register Maps
      1. 7.6.1 GRAYSCALE Registers
        1. 7.6.1.1 OUTn_GS Register (Offset = 0h)
          1. Table 25. OUTn_GS Register Field Descriptions
      2. 7.6.2 FC-BC-DC Registers
        1. 7.6.2.1 FC-BC-DC Register (Offset = 1h)
          1. Table 28. FC-BC-DC Register Field Descriptions
      3. 7.6.3 SID Registers
        1. 7.6.3.1 SID Register (Offset = 2h)
          1. Table 31. SID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tro0 Rise time from 10% VSDO to 90% VSDO 60 ns
tro1 Rise time from 10% VOUT to 90% VOUT IOUT = 50 mA, SLEW_RATE = 0b 200 ns
tro2 Rise time from 10% VOUT to 90% VOUT IOUT = 50 mA, SLEW_RATE = 1b 60 100 140 ns
tfo0 Fall time from 90% VSDO to 10% VSDO 30 ns
tfo1 Fall time from 90% VOUT to 10% VOUT IOUT = 50 mA , SLEW_RATE = 0b 200 ns
tfo2 Fall time from 90% VOUT to 10% VOUT IOUT = 50 mA, SLEW_RATE = 1b 30 80 130 ns
tpd0 Propagation delay, SCK↑to SDO 100 140 200 ns
tpd1 Propagation delay, LATCH↑to SDO 130 180 220 ns
tpd2 Propagation delay, BLANK↓ to OUTR0, -G0, -B0, -R4, -G4, -B4 off 10 120 260 ns
tpd3 Propagation delay, GCLK↑ to OUTR0, -G0, -B0, -R4, -G4,-B4 on 80 160 260 ns
tpd4 Propagation delay, GCLK↑ to OUTR1, -G1, -B1, -R5, -G5, -B5 on 120 200 330 ns
tpd5 Propagation delay, GCLK↑ to OUTR2, -G2, -B2, -R6, -G6, -B6 on 160 250 370 ns
tpd6 Propagation delay, GCLK↑ to OUTR3, -G3, -B3, -R7, -G7, -B7 on 190 280 400 ns
tpd7 Propagation delay, LATCH↑ to VOUT Changing by dot correction control (control data are 0Ch→72h or 72h→0Ch with upper DC range), BCR, -G, -B = FFh 10 80 120 ns
tpd8 Propagation delay, LATCH↑ to VOUT Changing by global brightness control (control data are 19h→E6h or E6h→19h with DCRn,-Gn, -Bn = 7Fh with upper DC range 10 130 200 ns
tpd9 Propagation delay, LATCH↑ to APS register and APS_FLAG change SINK_CURRENT = 0b 5 ns
tpd10 Propagation delay, LATCH↑ to APS register and APS_FLAG change SINK_CURRENT = 1b 10 ns
tpd11 Propagation delay, LATCH↑ to LOD_LSD_FLAG change No failure in LOD-LSD detector circuit 24 ns
TLC6C5724-Q1 GS-write-slasek2.gifFigure 1. Grayscale (GS) Data Write
TLC6C5724-Q1 DC-write-slasek2.gifFigure 2. Function Control, Brightness Control, and Dot Correction Data (FC-BC-DC) Write
TLC6C5724-Q1 GS-read-slasek2.gifFigure 3. Grayscale (GS) Data Read
TLC6C5724-Q1 SID-read-slasek2.gifFigure 4. Status Information Data (SID) Read
TLC6C5724-Q1 APS-slasek2.gifFigure 5. Adjacent-Pin-Short (APS) Check
TLC6C5724-Q1 Negate-slasek2.gifFigure 6. Negate Bit Toggle
TLC6C5724-Q1 LOD-Self-Test-slasek2.gifFigure 7. LOD_LSD Self-Test
TLC6C5724-Q1 Read-FC-slasek2.gifFigure 8. Function Control, Brightness Control, and Dot Correction Data (FC-BC-DC) Read
TLC6C5724-Q1 Reset-Error-slasek2.gifFigure 9. ERROR Clear
TLC6C5724-Q1 Global-Reset-slasek2.gifFigure 10. Global Reset
TLC6C5724-Q1 12-Bit-PWM-without-Auto-Repeat-slasek2.gifFigure 11. 12-Bit Mode PWM Counter Without Auto-Repeat Mode
TLC6C5724-Q1 8-10-12-bit-mode-without-auto-repeat-mode-slasek2.gifFigure 12. 8-, 10-, 12-Bit Mode PWM Counter Without Auto-Repeat Mode
TLC6C5724-Q1 Auto-Repeat-slasek2.gifFigure 13. 8-, 10-, 12-Bit Mode PWM Counter With Auto-Repeat Mode
TLC6C5724-Q1 LOD-LSD-Update-slasek2.gifFigure 14. LOD-LSD Register Update Timing