JAJSF71D
April 2018 – June 2022
TLIN1024-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
ESD Ratings - IEC
6.4
Thermal Information
6.5
Recommended Operating Conditions
6.6
Electrical Characteristics
6.7
Switching Characteristics (1)
6.8
Timing Requirements
Typical Characteristics
Parameter Measurement Information
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
LIN (Local Interconnect Network) Bus
7.3.1.1
LIN Transmitter Characteristics
7.3.1.2
LIN Receiver Characteristics
7.3.1.2.1
Termination
7.3.2
TXD (Transmit Input/Output)
7.3.3
RXD (Receive Output)
7.3.4
VSUP1/2 (Supply Voltage)
7.3.5
GND (Ground)
7.3.6
EN (Enable Input)
7.3.7
Protection Features
7.3.8
TXD Dominant Time Out (DTO)
7.3.9
Bus Stuck Dominant System Fault: False Wake Up Lockout
7.3.10
Thermal Shutdown
7.3.11
Under Voltage on VSUP
7.3.12
Unpowered Device and LIN Bus
7.4
Device Functional Modes
7.4.1
Normal Mode
7.4.2
Sleep Mode
7.4.3
Standby Mode
7.4.4
Wake Up Events
7.4.4.1
Wake Up Request (RXD)
7.4.4.2
Mode Transitions
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Normal Mode Application Note
8.2.2.2
Standby Mode Application Note
8.2.2.3
TXD Dominant State Timeout Application Note
8.2.3
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
サポート・リソース
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RGY|24
MPQF143E
サーマルパッド・メカニカル・データ
RGY|24
QFND581
発注情報
jajsf71d_oa
jajsf71d_pm
7
Parameter Measurement Information
Figure 7-1
Test System: Operating Voltage Range with RX and TX Access
Figure 7-2
RX Response: Operating Voltage Range
Figure 7-3
LIN Bus Input Signal
Figure 7-4
LIN Receiver Test with RX Access
Figure 7-5
V
SUP_NON_OP
Figure 7-6
Test Circuit for I
BUS_LIM
at Dominant State (Driver on)
Figure 7-7
Test Circuit for I
BUS_PAS_dom
; TXD = Recessive State V
BUS
= 0 V
Figure 7-8
Test Circuit for I
BUS_PAS_rec
Figure 7-9
Test Circuit for I
BUS_NO_GND
Loss of GND
Figure 7-10
Test Circuit for I
BUS_NO_BAT
Loss of Battery
Figure 7-11
Test Circuit Slope Control and Duty Cycle
Figure 7-12
Definition of Bus Timing Parameters
Figure 7-13
Propagation Delay Test Circuit
Figure 7-14
Propagation Delay
Figure 7-15
Mode Transitions
Figure 7-16
Wake Up Through EN
Figure 7-17
Wake Up Through LIN
Figure 7-18
Test Circuit for AC Characteristics