JAJSF71D April   2018  – June 2022 TLIN1024-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings - IEC
    4. 6.4 Thermal Information
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Electrical Characteristics
    7. 6.7 Switching Characteristics (1)
    8. 6.8 Timing Requirements
    9.     Typical Characteristics
      1.      Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  LIN (Local Interconnect Network) Bus
        1. 7.3.1.1 LIN Transmitter Characteristics
        2. 7.3.1.2 LIN Receiver Characteristics
          1. 7.3.1.2.1 Termination
      2. 7.3.2  TXD (Transmit Input/Output)
      3. 7.3.3  RXD (Receive Output)
      4. 7.3.4  VSUP1/2 (Supply Voltage)
      5. 7.3.5  GND (Ground)
      6. 7.3.6  EN (Enable Input)
      7. 7.3.7  Protection Features
      8. 7.3.8  TXD Dominant Time Out (DTO)
      9. 7.3.9  Bus Stuck Dominant System Fault: False Wake Up Lockout
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Under Voltage on VSUP
      12. 7.3.12 Unpowered Device and LIN Bus
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Mode
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Standby Mode
      4. 7.4.4 Wake Up Events
        1. 7.4.4.1 Wake Up Request (RXD)
        2. 7.4.4.2 Mode Transitions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Normal Mode Application Note
        2. 8.2.2.2 Standby Mode Application Note
        3. 8.2.2.3 TXD Dominant State Timeout Application Note
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The TLIN1024-Q1 device is a Quad Local Interconnect Network (LIN) physical layer transceiver, compliant to LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4.2, with integrated wake-up and protection features. The TLIN1024-Q1 has two separate dual LIN transceiver blocks. VSUP1/2 provides power to the separate dual transceiver blocks. The LIN bus is a single wire bidirectional bus typically used for low speed in vehicle networks using data rates up to 20 kbps. The TLIN1024-Q1 LIN receivers work up to 100 kbps supporting in-line programming. The LIN protocol output data stream on the TXD in converted by the TLIN1024-Q1 into LIN bus signal using a current-limited wave shaping driver as outlined by the LIN physical layer specification. The receiver converts the data stream to logic level signals that are sent to the microprocessor through the open drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external pull-up components are required for responder applications. Commander applications require an external pull-up resistor (1 kΩ) plus a series diode per the LIN specification. The TLIN1024-Q1 provides many protection features such as ESD, EMC and high bus standoff voltage.

The TLIN1024-Q1 support wide operating ranges with VSUP1/2 of 4 V to 36 V, ±45 V LIN bus fault protection, -40 to +125 C TA. Sleep mode is supported which is Ultra-Low current consumption. There are two methods to wake up the TLIN1024-Q1 from sleep mode; by the LIN bus and local wake-up using the EN pin. The TLIN1024-Q1 provides protection features that include ±8 kV HBM and IEC ESD protection on LIN pins, under voltage protection on VSUP1/2, TXD dominant time out protection (DTO), thermal shutdown protection and unpowered node or ground disconnection failsafe at system level. VSUP1 and GND1 supplies transceivers 1 and 2 while VSUP2 and GND2 supplies transceiver 3 and 4. The TLIN1024-Q1 is part of the LIN family that includes the TLIN1022 and TLIN1029 LIN transceivers.