JAJSK69A December 2020 – April 2022 TLIN1029A-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Power Supply | ||||||
VSUP | Operational supply voltage (ISO/DIS 17987 Param 10) | Device is operational beyond the LIN defined nominal supply voltage range See Figure 8-1 and Figure 8-2 | 4 | 36 | V | |
VSUP | Nominal supply voltage (ISO/DIS 17987 Param 10) | Normal and Standby Modes: ramp VSUP while LIN signal is a 10 kHz square wave with 50 % duty cycle and 36V swing. See Figure 8-1 and Figure 8-2 | 4 | 36 | V | |
Sleep Mode | 4 | 36 | V | |||
UVSUP | Under voltage VSUP threshold | Min is falling edge and Max is rising edge | 2.9 | 3.85 | V | |
UVHYS | Delta hysteresis voltage for VSUP under voltage threshold | 0.2 | V | |||
ISUP | Supply current | Normal Mode: EN = high, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF | 1 | 5 | mA | |
Standby Mode: EN = low, bus dominant: total bus load where RLIN > 500 Ω and CLIN < 10 nF | 1 | 2.1 | mA | |||
ISUP | Supply current | Normal Mode: EN = high, bus recessive (LIN = VSUP) | 300 | 650 | µA | |
Standby Mode: EN = low, bus recessive (LIN = VSUP) | 10 | 30 | µA | |||
Sleep Mode: 4.0 V < VSUP ≤ 14 V, LIN = VSUP, EN = 0 V, TXD and RXD floating | 8 | 12 | µA | |||
Sleep Mode: 14 V < VSUP ≤ 36 V, LIN = VSUP, EN = 0 V, TXD and RXD floating | 20 | µA | ||||
TSD | Thermal shutdown | 165 | ℃ | |||
TSD(HYS) | Thermal shutdown hysteresis | 15 | ℃ | |||
RXD Output Pin (Open Drain) | ||||||
VOL | Output low voltage | Based upon external pull-up to VCC (4) | 0.6 | V | ||
IOL | Low level output current, open drain | LIN = 0 V, RXD = 0.4 V | 1.5 | mA | ||
IILG | Leakage current, high-level | LIN = VSUP, RXD = 5 V | –5 | 0 | 5 | µA |
TXD Input Pin | ||||||
VIL | Low level input voltage | –0.3 | 0.8 | V | ||
VIH | High level input voltage | 2 | 5.25 | V | ||
IILG | Low level input leakage current | TXD = low | –5 | 0 | 5 | µA |
RTXD | Internal pull-down resistor value | 125 | 350 | 800 | kΩ | |
LIN PIN | ||||||
VOH | LIN recessive high-level output voltage (3) | TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 36 V | 0.85 | VSUP | ||
VOH | LIN recessive high-level output voltage (1) (2) | TXD = high, IO = 0 mA, 7 V ≤ VSUP ≤ 18 V | 0.8 | VSUP | ||
VOH | LIN recessive high-level output voltage (3) | TXD = high, IO = 0 mA, 4 V ≤ VSUP < 7 V | 3 | V | ||
VOL | LIN dominant low-level output voltage (3) | TXD = low, 7 V ≤ VSUP ≤ 36 V | 0.2 | VSUP | ||
VOL | LIN dominant low-level output voltage (1) (2) | TXD = low, 7 V ≤ VSUP ≤ 18 V | 0.2 | VSUP | ||
VOL | LIN dominant low-level output voltage (3) | TXD = low, 4 V ≤ VSUP < 7 V | 1.2 | V | ||
VSUP_NON_OP | VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) | TXD & RXD open LIN = 4 V to 45 V | –0.3 | 45 | V | |
IBUS_LIM | Limiting current (ISO/DIS 17987 Param 12) | TXD = 0 V, VLIN = 18 V, VSUP = 18 V | 40 | 90 | 200 | mA |
IBUS_PAS_dom | Receiver leakage current, dominant (ISO/DIS 17987 Param 13) | LIN = 0 V, VSUP = 12 V Driver off/recessive Figure 8-6 | –1 | mA | ||
IBUS_PAS_rec1 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14) | LIN > VSUP, 4 V ≤ VSUP ≤ 36 V Driver off; Figure 8-7 | 20 | µA | ||
IBUS_PAS_rec2 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14) | LIN = VSUP, Driver off; Figure 8-7 | –5 | 5 | µA | |
IBUS_NO_GND | Leakage current, loss of ground (ISO/DIS 17987 Param 15) | GND = VSUP, VSUP = 18 V, RMeas = 1 kΩ, 0 V < VLIN < 18 V; Figure 8-8 | –1 | 1 | mA | |
Ileak gnd(dom) | Leakage current, loss of ground (5) | VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCommander = 1 kΩ, CL = 1 nF RResponder = 20 kΩ, CL = 1 nF LIN = dominant |
-1 | 1 | mA | |
Ileak gnd(rec) | Leakage current, loss of ground (5) | VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCommander = 1 kΩ, CL = 1 nF RResponder = 20 kΩ, CL = 1 nF LIN = recessive |
-100 | 100 | µA | |
IBUS_NO_BAT | Leakage current, loss of supply (ISO/DIS 17987 Param 16) | LIN = 18 V, VSUP = GND; Figure 8-9 | 5 | µA | ||
VBUSdom | Low level input voltage (ISO/DIS 17987 Param 17) (3) | LIN dominant (including LIN dominant for wake up) See Figure 8-4, Figure 8-3 | 0.4 | VSUP | ||
VBUSrec | High level input voltage (ISO/DIS 17987 Param 18) (3) | LIN recessive See Figure 8-4, Figure 8-3 | 0.6 | VSUP | ||
VIH | LIN recessive high-level input voltage (1) (2) | 7 V ≤ VSUP ≤ 18 V | 0.47 | 0.6 | VSUP | |
VIL | LIN dominant low-level input voltge (1) (2) | 7 V ≤ VSUP ≤ 18 V | 0.4 | 0.53 | VSUP | |
VBUS_CNT | Receiver center threshold (ISO/DIS 17987 Param 19) | VBUS_CNT = (VBUSrec + VBUSdom)/2 See Figure 8-4, Figure 8-3 | 0.475 | 0.5 | 0.525 | VSUP |
VHYS | Hysteresis voltage (ISO/DIS 17987 Param 20) | VHYS = (VBUSrec - VBUSdom) See Figure 8-4, Figure 8-3 | 0.175 | VSUP | ||
VHYS | Hysteresis voltage (SAE J2602) | VHYS = VIH - VIL See Figure 8-4, Figure 8-3 | 0.07 | 0.175 | VSUP | |
VSERIAL_DIODE | Serial diode LIN termination pull-up path | ISERIAL_DIODE = 10 μA | 0.4 | 0.7 | 1 | V |
RPU | Internal pull-up resistor to VSUP | Normal and standby modes | 20 | 45 | 60 | kΩ |
IRSLEEP | Pull-up current source to VSUP | Sleep mode, VSUP = 14 V, LIN = GND | –20 | –2 | µA | |
CLINPIN | Capacitance of the LIN pin | VSUP = 14 V | 25 | pF | ||
EN Input Pin | ||||||
VIL | Low level input voltage | –0.3 | 0.8 | V | ||
VIH | High level input voltage | 2 | 5.25 | V | ||
VIT | Hysteresis voltage | By design and characterization | 50 | 500 | mV | |
IILG | Low level input current | EN = low | –5 | 0 | 5 | µA |
REN | Internal pull-down resistor | 125 | 350 | 800 | kΩ |