SLLSE75B May   2011  – July 2016 TLK10002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  10-Gbps Power Characteristics - 1.0 V
    6. 7.6  10-Gbps Power Characteristics - 1.5 V
    7. 7.7  10-Gbps Power Characteristics - 1.8 V
    8. 7.8  Transmitter and Receiver Characteristics
    9. 7.9  MDIO Timing Requirements
    10. 7.10 JTAG Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Speed Side Receiver Jitter Tolerance
      2. 8.3.2  Lane Alignment Scheme
      3. 8.3.3  Lane Alignment Components
      4. 8.3.4  Lane Alignment Operation
      5. 8.3.5  Channel Synchronization
      6. 8.3.6  Line Rate, SERDES PLL Settings, and Reference Clock Selection
      7. 8.3.7  Clocking Architecture
      8. 8.3.8  Loopback Modes
      9. 8.3.9  Deep Remote Loopback
      10. 8.3.10 Shallow Remote Loopback and Serial Retime
      11. 8.3.11 Deep Local Loopback
      12. 8.3.12 Shallow Local Loopback
      13. 8.3.13 Test Pattern Generation and Verification
      14. 8.3.14 Latency Measurement Function
      15. 8.3.15 Power-Down Mode
      16. 8.3.16 High Speed CML Output
      17. 8.3.17 High Speed Receiver
      18. 8.3.18 Loss of Signal Indication (LOS)
      19. 8.3.19 MDIO Management Interface
      20. 8.3.20 MDIO Protocol Timing
      21. 8.3.21 Clause 22 Indirect Addressing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Transmit (Low Speed to High Speed) Data Path
      2. 8.4.2 Receive (High Speed to Low Speed) Data Path
      3. 8.4.3 1:1 Retime Mode
    5. 8.5 Programming
      1. 8.5.1 Power Sequencing Guidelines
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Initialization Setup
      1. 9.3.1 4:1 Mode (9.8304 Gbps on HS Side, 2.4576 Gbps Per Lane on LS Side)
      2. 9.3.2 2:1 Mode (9.8304 Gbps on HS Side, 4.9152 Gbps Per Lane on LS Side, Only Lanes 0 and 1 on LS Side Active)
      3. 9.3.3 1:1 Mode (4.9152 Gbps on HS Side, 4.9152Gbps on LS side, Only Lane 0 on LS Side Active)
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 AC Coupling
      2. 11.1.2 TLK10002 Clocks: REFCLK, CLKOUT - General Information
      3. 11.1.3 External Clock Connections
      4. 11.1.4 TLK10002 Control Pins and Interfaces
        1. 11.1.4.1 MDIO Interface
        2. 11.1.4.2 JTAG Interface
        3. 11.1.4.3 Unused Pins
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Layout

11.1 Layout Guidelines

Both low-speed side and high-speed side serial signals are referred to as high-speed signals for the purpose of this document as they support very high data rates. For that reason, take care to realize them on a printed-circuit board with signal integrity in mind. The high-speed data path CML input pins INA[3:0]P/INA[3:0]N, INB[3:0]P/INB[3:0]N, HSRXAP/HSRXAN, and HSRXBP/HSRXBN, and the CML output pins OUTA[3:0]P/OUTA[3:0]N, OUTB[3:0]P/OUTB[3:0]N, HSTXAP/HSTXAN, and HSTXBP/HSTXBN, have to be connected with loosely-coupled 100-Ω differential transmission lines. Differential intra-pair skew needs to be minimized to within ±1 mil. Inter-pair (lane-to-lane) skew for the low-speed signals can be as high as 30 UI. An example of FR-4 printed-circuit board (PCB) realization of such differential transmission lines in microstrip format is shown in Figure 35.

TLK10002 diff_microstrip_PCB_trace_geo_ex_sllse75.gif Figure 35. Differential Microstrip PCB Trace Geometry Example

To avoid impedance discontinuities the high-speed serial signals must be routed on a PCB on either the top or bottom PCB layers in microstrip format with no vias. If vias are unavoidable, an absolute minimum number of vias need to be used. The vias must be made to stretch through the entire PCB thickness (as shown in Figure 35) to connect microstrip traces on the top and bottom layers of the PCB so as to leave no via stubs that can severely impact the performance. If stripline traces are absolutely necessary, and if via back-drilling is not possible, then the routing layers should be chosen so as to have via stubs that are shorter than 10 mils.

All unused internal layer via pads on high-speed signal vias must be removed to further improve impedance matching. On the high-speed side, the HSRXAP/HSRXAN and HSRXBP/HSRXBN signals are more sensitive to impedance discontinuities introduced by vias than HSTXAP/HSTXAN and HSTXBP/HSTXBN signals. For that reason, if only some of those signals need to be routed with vias, then the latter must be routed with vias and the former with no vias.

TLK10002 ex_high_speed_PCB_traces_sllse75.gif Figure 36. Examples of High-Speed PCB Traces With Vias that Have No Via Stubs and No Via Pads on Internal Layers

To further improve on impedance matching, differential vias with neighboring ground vias can be used as shown in Figure 37. The optimum dimensions of such a differential via structure depend on various parameters such as the trace geometry, dielectric material, as well as the PCB layer stack-up. A 3D electromagnetic field solver can be used to find the optimum via dimensions.

TLK10002 diff_PCB_via_structure_sllse75.gif Figure 37. A Differential PCB Via Structure (Top View)

PCB traces connected to the HSRXAP/HSRXAN and HSRXBP/HSRXBN pins must have differential insertion loss of less than 25 dB at 5 GHz.

Surface-mount connector pads such as those used with the SFP/SFP+ module connectors are wider and hence have characteristic impedance that is lower than the regular high-speed PCB traces. If the pads are more than 2 times wider than the PCB traces, the pads’ impedance needs to be increased to minimize impedance discontinuities. The easy way of increasing the pads’ impedance is to cut out the reference plane immediately under those pads as shown in Figure 38 so as to have the pads refer to a reference plane on lower layers while maintaining 100-Ω differential characteristic impedance.

TLK10002 ref_plane_cut_out_under_SFP_SFP_sllse75.gif Figure 38. Reference Plane Cut-Out Under SFP/SFP+ Module Connector Pads

11.1.1 AC Coupling

A 0.1-µF series AC-coupling capacitor must be connected to each of the high-speed data path pins INA[3:0]P/INA[3:0]N, INB[3:0]P/INB[3:0]N, HSRXAP/HSRXAN, HSRXBP/HSRXBN, OUTA[3:0]P/OUTA[3:0]N, OUTB[3:0]P/OUTB[3:0]N, HSTXAP/HSTXAN, and HSTXBP/HSTXBN. If the TLK10002 high-speed side data path pins are connected to SFP/SFP+ optical modules with internal AC-coupling capacitors, then no external capacitors should be used. Adding additional series capacitors may severely impact the performance.

To avoid impedance discontinuities, TI strongly recommends where possible to make the transmission line trace width closely match the AC-coupling capacitor pad size. Smaller capacitor packages such as 0201 make it easy to meet that condition.

11.1.2 TLK10002 Clocks: REFCLK, CLKOUT – General Information

The TLK10002 device requires a low-jitter reference clock to work. The reference clock can be provided on the REFCLK0P/N or REFCLK1P/N pins. Both reference clock input pins have internal 100-Ω differential terminations, so they do not need any external terminations. Both reference clock inputs must be AC-coupled with preferably 0.1-µF capacitors. The two channels (A and B) can have same or different reference clocks.

The TLK10002 serial receiver recovers clock and data from the incoming serial data. The recovered byte clock is made available on the CLKOUTAP/N and/or CLKOUTBP/N pins. The CLKOUTxP/N CML output pins must be AC-coupled with 0.1-µF AC-coupling capacitors.

11.1.3 External Clock Connections

An external clock jitter cleaner, such as Texas Instruments CDCE72010 or CDCM7005, may be used when needed to provide a low jitter reference clock. An example external clock jitter cleaner connection for channel A is shown in Figure 39.

TLK10002 external_clock_jitter_cleaner_conn_sllse75.gif Figure 39. An External Clock Jitter Cleaner Connection Example for Channel A

11.1.4 TLK10002 Control Pins and Interfaces

The TLK10002 device features a number of control pins and interfaces, some of which are described below.

11.1.4.1 MDIO Interface

The TLK10002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the serial links.

The MDIO Management Interface consists of a bidirectional data path (MDIO) and a clock reference (MDC). The port address is determined by the PRTAD[4:0] control pins.

The MDIO pin requires a pullup to VDDO[1:0]. No pullup is needed on the MDC pin if driven with a push-pull MDIO master, but a pullup to VDDO[1:0] is needed if driven with an open-drain MDIO master.

11.1.4.2 JTAG Interface

The JTAG interface is mostly used for device test. The JTAG interface operates through the TDI, TDO, TMS, TCK, and TRST_N pins. If not used, all the pins can be left unconnected except TDI and TCK which have to be grounded.

11.1.4.3 Unused Pins

As a general guideline, any unused LVCMOS input pin needs to be grounded and any unused LVCMOS output pin can be left unconnected. Unused CML differential output pins can be left unconnected. Unused CML differential input pins should be tied to ground through a shared 100-Ω resistor.

11.2 Layout Example

TLK10002 layout_sllse75.gif Figure 40. Board-to-Board Connector Pinout and Routing