SLLSEE3D August   2013  – April 2016 TLK105L , TLK106L

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Serial Management Interface (SMI)
    3. 3.3 MAC Data Interface
    4. 3.4 10Mbs and 100Mbs PMD Interface
    5. 3.5 Clock Interface
    6. 3.6 LED Interface
    7. 3.7 Reset and Power Down
    8. 3.8 Power and Bias Connections
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 20
      1. 4.4.1 TLK105L 32-Pin Industrial Device (85°C) Thermal Characteristics
    5. 4.5 TLK106L 32-Pin Extended Temperature (105°C) Device Thermal Characteristics
    6. 4.6 DC Characteristics, VDD_IO
    7. 4.7 DC Characteristics
    8. 4.8 Power Supply Characteristics
      1. 4.8.1 Active Power, Single Supply Operation
      2. 4.8.2 Active Power, Dual Supply Operation
      3. 4.8.3 Power-Down Power
    9. 4.9 AC Specifications
      1. 4.9.1  Power Up Timing
      2. 4.9.2  Reset Timing
      3. 4.9.3  MII Serial Management Timing
      4. 4.9.4  100Mb/s MII Transmit Timing
      5. 4.9.5  100Mb/s MII Receive Timing
      6. 4.9.6  100Base-TX Transmit Packet Latency Timing
      7. 4.9.7  100Base-TX Transmit Packet Deassertion Timing
      8. 4.9.8  100Base-TX Transmit Timing (tR/F and Jitter)
      9. 4.9.9  100Base-TX Receive Packet Latency Timing
      10. 4.9.10 100Base-TX Receive Packet Deassertion Timing
      11. 4.9.11 10Mbs MII Transmit Timing
      12. 4.9.12 10Mb/s MII Receive Timing
      13. 4.9.13 10Base-T Transmit Timing (Start of Packet)
      14. 4.9.14 10Base-T Transmit Timing (End of Packet)
      15. 4.9.15 10Base-T Receive Timing (Start of Packet)
      16. 4.9.16 10Base-T Receive Timing (End of Packet)
      17. 4.9.17 10Mb/s Jabber Timing
      18. 4.9.18 10Base-T Normal Link Pulse Timing
      19. 4.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
      20. 4.9.20 100Base-TX Signal Detect Timing
      21. 4.9.21 100Mbs Loopback Timing
      22. 4.9.22 10Mbs Internal Loopback Timing
      23. 4.9.23 RMII Transmit Timing
      24. 4.9.24 RMII Receive Timing
      25. 4.9.25 Isolation Timing
  5. 5Detailed Description
    1. 5.1 Hardware Configuration
      1. 5.1.1  Bootstrap Configuration
      2. 5.1.2  Power Supply Configuration
        1. 5.1.2.1 Single Supply Operation
        2. 5.1.2.2 Dual Supply Operation
        3. 5.1.2.3 Variable IO Voltage
      3. 5.1.3  IO Pins Hi-Z State During Reset
      4. 5.1.4  Auto-Negotiation
      5. 5.1.5  Auto-MDIX
      6. 5.1.6  MII Isolate Mode
      7. 5.1.7  PHY Address
      8. 5.1.8  LED Interface
      9. 5.1.9  Loopback Functionality
        1. 5.1.9.1 Near-End Loopback
        2. 5.1.9.2 Far-End Loopback
      10. 5.1.10 BIST
      11. 5.1.11 Cable Diagnostics
        1. 5.1.11.1 TDR
        2. 5.1.11.2 ALCD
    2. 5.2 Architecture
      1. 5.2.1 100Base-TX Transmit Path
        1. 5.2.1.1 MII Transmit Error Code Forwarding
        2. 5.2.1.2 4-Bit to 5-Bit Encoding
        3. 5.2.1.3 Scrambler
        4. 5.2.1.4 NRZI and MLT-3 Encoding
        5. 5.2.1.5 Digital to Analog Converter
      2. 5.2.2 100Base-TX Receive Path
        1. 5.2.2.1  Analog Front End
        2. 5.2.2.2  Adaptive Equalizer
        3. 5.2.2.3  Baseline Wander Correction
        4. 5.2.2.4  NRZI and MLT-3 Decoding
        5. 5.2.2.5  Descrambler
        6. 5.2.2.6  5B/4B Decoder and Nibble Alignment
        7. 5.2.2.7  Timing Loop and Clock Recovery
        8. 5.2.2.8  Phase-Locked Loops (PLL)
        9. 5.2.2.9  Link Monitor
        10. 5.2.2.10 Signal Detect
        11. 5.2.2.11 Bad SSD Detection
      3. 5.2.3 10Base-T Receive Path
        1. 5.2.3.1 10M Receive Input and Squelch
        2. 5.2.3.2 Collision Detection
        3. 5.2.3.3 Carrier Sense
        4. 5.2.3.4 Jabber Function
        5. 5.2.3.5 Automatic Link Polarity Detection and Correction
        6. 5.2.3.6 10Base-T Transmit and Receive Filtering
        7. 5.2.3.7 10Base-T Operational Modes
      4. 5.2.4 Auto Negotiation
        1. 5.2.4.1 Operation
        2. 5.2.4.2 Initialization and Restart
        3. 5.2.4.3 Next Page Support
      5. 5.2.5 Link Down Functionality
      6. 5.2.6 IEEE 1588 Precision Timing Protocol Support
    3. 5.3 Register Maps
      1. 5.3.1  Register Definition
        1. 5.3.1.1  Basic Mode Control Register (BMCR)
        2. 5.3.1.2  Basic Mode Status Register (BMSR)
        3. 5.3.1.3  PHY Identifier Register 1 (PHYIDR1)
        4. 5.3.1.4  PHY Identifier Register 2 (PHYIDR2)
        5. 5.3.1.5  Auto-Negotiation Advertisement Register (ANAR)
        6. 5.3.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.3.1.7  Auto-Negotiate Expansion Register (ANER)
        8. 5.3.1.8  Auto-Negotiate Next Page Transmit Register (ANNPTR)
        9. 5.3.1.9  Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
        10. 5.3.1.10 Control register 1 (CR1)
        11. 5.3.1.11 Control register 2 (CR2)
        12. 5.3.1.12 Control Register 3 (CR3)
        13. 5.3.1.13 Extended Register Addressing
          1. 5.3.1.13.1 Register Control Register (REGCR)
          2. 5.3.1.13.2 Address or Data Register (ADDAR)
        14. 5.3.1.14 Fast Link Down Status Register
        15. 5.3.1.15 PHY Status Register (PHYSTS)
        16. 5.3.1.16 PHY Specific Control Register (PHYSCR)
        17. 5.3.1.17 MII Interrupt Status Register 1 (MISR1)
        18. 5.3.1.18 MII Interrupt Status Register 2 (MISR2)
        19. 5.3.1.19 False Carrier Sense Counter Register (FCSCR)
        20. 5.3.1.20 Receiver Error Counter Register (RECR)
        21. 5.3.1.21 BIST Control Register (BISCR)
        22. 5.3.1.22 RMII Control and Status Register (RCSR)
        23. 5.3.1.23 LED Control Register (LEDCR)
        24. 5.3.1.24 PHY Control Register (PHYCR)
        25. 5.3.1.25 10Base-T Status/Control Register (10BTSCR)
        26. 5.3.1.26 BIST Control and Status Register 1 (BICSR1)
        27. 5.3.1.27 BIST Control and Status Register2 (BICSR2)
      2. 5.3.2  Cable Diagnostic Control Register (CDCR)
      3. 5.3.3  PHY Reset Control Register (PHYRCR)
      4. 5.3.4  Multi LED Control register (MLEDCR)
      5. 5.3.5  Compliance Test register (COMPTR)
      6. 5.3.6  IEEE1588 Precision Timing Pin Select (PTPPSEL)
      7. 5.3.7  IEEE1588 Precision Timing Configuration (PTPCFG)
      8. 5.3.8  TX_CLK Phase Shift Register (TXCPSR)
      9. 5.3.9  Power Back Off Control Register (PWRBOCR)
      10. 5.3.10 Voltage Regulator Control Register (VRCR)
      11. 5.3.11 Cable Diagnostic Configuration/Result Registers
        1. 5.3.11.1  ALCD Control and Results 1 (ALCDRR1)
        2. 5.3.11.2  Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
        3. 5.3.11.3  Cable Diagnostic Location Results Register 1 (CDLRR1)
        4. 5.3.11.4  Cable Diagnostic Location Results Register 2 (CDLRR2)
        5. 5.3.11.5  Cable Diagnostic Location Results Register 3 (DDLRR3)
        6. 5.3.11.6  Cable Diagnostic Location Results Register 4 (CDLRR4)
        7. 5.3.11.7  Cable Diagnostic Location Results Register 5 (CDLRR5)
        8. 5.3.11.8  Cable Diagnostic Amplitude Results Register 1 (CDARR1)
        9. 5.3.11.9  Cable Diagnostic Amplitude Results Register 2 (CDARR2)
        10. 5.3.11.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)
        11. 5.3.11.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)
        12. 5.3.11.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)
        13. 5.3.11.13 Cable Diagnostic General Results Register (CDGRR)
        14. 5.3.11.14 ALCD Control and Results 2 (ALCDRR2)
        15. 5.3.11.15 ALCD Control and Results 3 (ALCDRR3)
  6. 6Applications, Implementation, and Layout
    1. 6.1 Interfaces
      1. 6.1.1 Media Independent Interface (MII)
      2. 6.1.2 Reduced Media Independent Interface (RMII)
      3. 6.1.3 Serial Management Interface
        1. 6.1.3.1 Extended Address Space Access
          1. 6.1.3.1.1 Write Address Operation
          2. 6.1.3.1.2 Read Address Operation
          3. 6.1.3.1.3 Write (no post increment) Operation
          4. 6.1.3.1.4 Read (no post increment) Operation
          5. 6.1.3.1.5 Write (post increment) Operation
          6. 6.1.3.1.6 Read (post increment) Operation
    2. 6.2 Reset and Power-Down Operation
      1. 6.2.1 Hardware Reset
      2. 6.2.2 Software Reset
      3. 6.2.3 Power Down/Interrupt
        1. 6.2.3.1 Power Down Control Mode
        2. 6.2.3.2 Interrupt Mechanisms
      4. 6.2.4 Power Save Modes
    3. 6.3 Design Guidelines
      1. 6.3.1 TPI Network Circuit
      2. 6.3.2 Clock In (XI) Requirements
        1. 6.3.2.1 Oscillator
        2. 6.3.2.2 Crystal
      3. 6.3.3 Thermal Vias Recommendation
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
    2. 7.2 Related Links
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

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6 Applications, Implementation, and Layout

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Interfaces

6.1.1 Media Independent Interface (MII)

The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22.

The MII signals are summarized below.

Data signals TXD [3:0]
RXD [3:0]
Transmit and receive-valid signals TX_EN
RX_DV
Line-status signals CRS (carrier sense)
COL (collision) (By default, the COL pin is disabled, and can be configured to be enabled instead of LED_LINK using bit [10] in register 0x0025).

Figure 6-1 shows the MII-mode signals.

TLK105L TLK106L mii_sig_lls901.gifFigure 6-1 MII Signaling

The Isolate bit (BMCR register bit 10), defined in IEEE802.3-2002, electrically isolates the PHY from the MII (if set, all transactions on the MII interface are ignored by the PHY).

Additionally, the MII interface includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both transmit and receive operation occur simultaneously.

6.1.2 Reduced Media Independent Interface (RMII)

TLK10xL incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII.

The RMII specification has the following characteristics:

  • Supports 10Mbs and 100Mbs data rates
  • Single clock reference sourced from the MAC to PHY (or from an external source)
  • Provides independent 2 bit wide (di-bit) transmit and receive data paths
  • Uses CMOS signal levels, operates at 3.3V or 2.5V VDD_IO levels

In this mode, data transfers two bits at a time using the 50MHz RMII reference clock for both transmit and receive. RMII mode uses the following pins:

SIGNAL PIN
XI (RMII reference clock is 50MHz) 23
TXD_0 4
TXD_1 5
TX_EN 3
CRS_DV 27
RX_ER 28
RXD_0 30
RXD_1 31

Data on TXD [1:0] are latched at the PHY with reference to the reference-clock edges on the XI pin. Data on RXD [1:0] are latched at the MAC with reference to the same reference clock edges on the XI pin. The RMII operates at the same speed (50MHz) in both 10B-T and 100B-TX. In 10B-T the data is 10 times slower than the reference clock, so transmit data is sampled every 10 clocks. Likewise, receive data is generated on every 10th clock so that an attached MAC device can sample the data every 10 clocks.

In addition, RMII mode supplies an RX_DV signal which allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though not required by RMII spec (The TLK10xL supports optional use of RX_ER and RX_DV in RMII as an extra feature). RMII mode requires a 50MHz oscillator connected to the device XI pin.

The TLK10xL supports a special mode called “RMII receive clock” mode. This mode, which is not part of the RMII specification, allows synchronization of the MAC-PHY RX interface. In this mode, the PHY generates a recovered 50MHz clock through the RX_CLK pin and synchronizes the RXD[1:0], CRS_DV, RX_DV and RX_ER signals to this clock. Setting register 0x000A bit [0] is required to activate this mode.

describes the RMII signals connectivity between the TLK10xL and any MAC device.

TLK105L TLK106L rmii_phy_mac.gif TLK10xL RMII/MAC Connection

RMII function includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal propagation delay based on expected maximum packet size and clock accuracy.

indicates how to program the buffer FIFO based on the expected max packet size and clock accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy.

Recommended RMII Packet Sizes

START THRESHOLD RBR[1:0] LATENCY TOLERANCE RECOMMENDED PACKET SIZE AT ±50PPM RECOMMENDED PACKET SIZE AT ±100PPM
1(4-bits) 2 bits 2400 bytes 1200 bytes
2(8-bits) 6 bits 7200 bytes 3600 bytes
3(12-bits) 10 bits 12000 bytes 6000 bytes
0(16-bits) 14 bits 16800 bytes 8400 bytes

6.1.3 Serial Management Interface

The Serial Management Interface (SMI), provides access to the TLK10xL internal register space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide additional visibility and controllability of the TLK10xL device.

The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle.

The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2kΩ) which, during IDLE and turnaround, pulls MDIO high.

Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power-up reset, the TLK10xL latches the PHYAD[4:0] configuration pins (Pin 29 to Pin 32) to determine its address.

The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de-asserted.

In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed TLK10xL drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 6-2 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the TLK10xL (PHY) for a typical register read access.

For write transactions, the station-management entity writes data to the addressed TLK10xL, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 6-3 shows the timing relationship for a typical MII register write access. The frame structure and general read/write transactions are shown in Table 6-1, Figure 6-2, and Figure 6-3.

Table 6-1 Typical MDIO Frame Format

MII MANAGEMENT SERIAL PROTOCOL <IDLE><START><OP CODE><DEVICE ADDR><REG ADDR><TURNAROUND><DATA><IDLE>
Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
TLK105L TLK106L MDC_read_llu119.gif Figure 6-2 Typical MDC/MDIO Read Operation
TLK105L TLK106L MDC_write_llu119.gif Figure 6-3 Typical MDC/MDIO Write Operation

6.1.3.1 Extended Address Space Access

The TLK10xL SMI function supports read/write access to the extended register set using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE802.3ah Draft for clause 22 for accessing the clause 45 extended register set.

The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the indirect method, except for register REGCR(0x000Dh) and ADDAR(0x000Eh) which is accessed only using the normal MDIO transaction. The SMI function will ignore indirect accesses to these registers.

REGCR(0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device address DEVAD that directs any accesses of ADDAR(0x000Eh) register to the appropriate MMD. Specifically, the TLK10xL uses the vendor-specific DEVAD[4:0] = "11111" for accesses. All accesses through registers REGCR and ADDAR must use this DEVAD. Transactions with other DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01), data with post increment on read and writes (10) and data with post increment on writes only (11).

  • ADDAR is the address/data MMD register. ADDAR is used in conjunction with REGCR to provide the access to the extended register set. If register REGCR[15:1] is 00, then ADDAR holds the address of the extended address space register. Otherwise, ADDAR holds the data as indicated by the contents of its address register. When REGCR[15:14] is set to 00, accesses to register ADDAR modify the extended register set address register. This address register must always be initialized in order to access any of the registers within the extended register set.
  • When REGCR[15:14] is set to 01, accesses to register ADDAR access the register within the extended register set selected by the value in the address register.
  • When REGCR[15:14] is set to 10, access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for both reads and writes, the value in the address register is incremented.
  • When REGCR[15:14] is set to 11, access to register ADDAR access the register within the extended register set selected by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the address register remains unchanged.

The following sections describe how to perform operations on the extended register set using register REGCR and ADDAR.

6.1.3.1.1 Write Address Operation

To set the address register:

  1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
  2. Write the desired register address to register ADDAR.

Subsequent writes to register ADDAR (step 2) continue to write the address register.

6.1.3.1.2 Read Address Operation

To read the address register:

  1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
  2. Read the register address from register ADDAR.

Subsequent reads to register ADDAR (step 2) continue to read the address register.

6.1.3.1.3 Write (no post increment) Operation

To write a register in the extended register set:

  1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
  2. Write the desired register address to register ADDAR.
  3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.
  4. Write the content of the desired extended register set register to register ADDAR.

Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the address register.

Note: steps (1) and (2) can be skipped if the address register was previously configured.

6.1.3.1.4 Read (no post increment) Operation

To read a register in the extended register set:

  1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
  2. Write the desired register address to register ADDAR.
  3. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR.
  4. Read the content of the desired extended register set register to register ADDAR.

Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the address register.

Note: steps (1) and (2) can be skipped if the address register was previously configured.

6.1.3.1.5 Write (post increment) Operation

  1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
  2. Write the register address from register ADDAR.
  3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) or the value 0xC01F (data, post increment on writes function field = 11. DEVAD = 31) to register REGCR.
  4. Write the content of the desired extended register set register to register ADDAR.

Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the value of the address register; the address register is incremented after each access.

6.1.3.1.6 Read (post increment) Operation

To read a register in the extended register set and automatically increment the address register to the next higher value following the write operation:

  1. Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR.
  2. Write the desired register address to register ADDAR.
  3. Write the value 0x801F (data, post increment on reads and writes function field = 10, DEVAD = 31) to register REGCR.
  4. Read the content of the desired extended register set register to register ADDAR.

Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the value of the address register; the address register is incremented after each access.

6.2 Reset and Power-Down Operation

The TLK10xL includes an internal power-on-reset (POR) function, and therefore does not need an explicit reset for normal operation after power up.

At power-up, if required by the system, the RESET pin (active low) should be de-asserted 200µs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize. If required during normal operation, the device can be reset by a hardware or software reset.

6.2.1 Hardware Reset

A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1μs, to RESET. This pulse resets the device such that all registers are reinitialized to default values, and the hardware configuration values are re-latched into the device (similar to the power-up/reset operation). The time from the point when the reset pin is de-asserted to the point when the reset has concluded internally is approximately 200µs.

6.2.2 Software Reset

An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (0x0000h). This bit only resets the IEEE-defined standard registers in the address space 0x00h to 0x07h.

A global software reset is accomplished by setting bit 15 of register PHYRCR (0x001F) to ‘1’. This bit resets all the internal circuits in the PHY including IEEE-defined registers (0x00h to 0x07h) and all the extended registers. The global software reset resets the device such that all registers are reset to default values and the hardware configuration values are maintained.

A global software restart is accomplished by setting bit 14 of register PHYRCR (0x001F) to ‘1’. This action resets all the PHY circuits except the registers in the Register File.

The time from the point when the resets/restart bits are set to the point when the software resets/restart has concluded is approximately 200µs. TI recommends that the software driver code must wait 500µs following software reset before allowing further serial MII operations with the TLK10xL.

6.2.3 Power Down/Interrupt

The Power Down and Interrupt functions are multiplexed on pin 8 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. This pin can be configured as an interrupt output pin by setting bit 0 (INT_OE) to ‘1’ in the PHYSCR (0x0011h) register. The PHYSCR register is also used to enable and set the polarity of the interrupt.

6.2.3.1 Power Down Control Mode

The INT/PWDN pin can be asserted low to put the device in a Power Down mode. An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the INT/PWDN pin.

6.2.3.2 Interrupt Mechanisms

The interrupt function is controlled via register access. All interrupt sources are disabled by default. The MISR1 (0x0012) and MISR2 (0x0013) registers provide independent interrupt enable bits for the various interrupts supported by the TLK10xL. The INT/PWDN pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the interrupt status registers MISR1 (0x0012h) and MISR2 (0x0013). One or more bits in the MISR registers will be set, indicating all currently-pending interrupts. Reading the MISR registers clears ALL pending interrupts.

6.2.4 Power Save Modes

The TLK10xL supports three types of power-save modes. The lowest power consumption is achieved in IEEE power down mode. To enter IEEE power down mode, pull the INT/PWDN pin to LOW or program bit 11 in the Basic Mode Control Register (BMCR), address 0x0000. In this mode all internal circuitry except SMI functionality is shut down (Register access is still available).

To enable and activate all other power save modes through register access, use register PHYSCR (0x0011h). Setting bit 14 enables all power-save modes; bits [13:12] select between them.

Setting bits [13:12] to “01” powers down the PHY, forcing it into IEEE power down mode (Similar to BMCR bit 11 functionality).

Setting bits [13:12] to “10” puts the PHY in Low Power Active Energy Saving mode.

Setting bits [13:12] to “11” puts the PHY in Low Power Passive Energy Saving mode.

When these bits are cleared, the PHY powers up and returns to the last state it was in before it was powered down.

6.3 Design Guidelines

6.3.1 TPI Network Circuit

Figure 6-4 shows the recommended circuit for a 10/100Mbs twisted pair interface. Common mode chokes on the device side of the transformer are required. Variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application.

TLK105L TLK106L twist_pair_if_lls901_update_req.gif Figure 6-4 10/100Mbs Twisted Pair Interface

6.3.2 Clock In (XI) Requirements

The TLK10xL supports an external CMOS-level oscillator source or an internal oscillator with an external crystal.

6.3.2.1 Oscillator

If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The oscillator should use the same supply voltage as the VDD_IO supply. When operating in RMII, the oscillator supply voltage must be 3.3V or 2.5V.

6.3.2.2 Crystal

The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 6-5 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW. If a crystal is specified for a lower drive level, a current limiting resistor must be placed in series between XO and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, set the values for CL1 and CL2 at 33pF, and R1 should be set at 0Ω. Specifications for a 25MHz crystal are listed in Table 6-4.

TLK105L TLK106L s0340-01_lls931.gif Figure 6-5 Crystal Oscillator Circuit

Table 6-2 25MHz Oscillator Specification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency 25 MHz
Frequency Tolerance Operational Temperature ±50 ppm
Frequency Stability 1 year aging ±50 ppm
Rise / Fall Time 10%–90% 8 nsec
Jitter (Short term) Cycle-to-cycle 50 psec
Jitter (Long term) Accumulative over 10 ms 1 nsec
Symmetry Duty Cycle 40% 60%
Load Capacitance 15 30 pF

Table 6-3 50MHz Oscillator Specification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency 50 MHz
Frequency Tolerance Operational Temperature ±50 ppm
Frequency Stability 1 year aging ±50 ppm
Rise / Fall Time 10%–90% 6 nsec
Jitter (Short term) Cycle-to-cycle 50 psec
Jitter (Long term) Accumulative over 10 ms 1 nsec
Symmetry Duty Cycle 40% 60%

Table 6-4 25MHz Crystal Specification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency 25 MHz
Frequency Tolerance Operational Temperature ±50 ppm
At 25°C ±50 ppm
Frequency Stability 1 year aging ±5 ppm
Load Capacitance 10 40 pF

6.3.3 Thermal Vias Recommendation

The following thermal via guidelines apply to DOWN_PAD, pin 33:

  1. Thermal via size = 0.2mm
  2. Recommend 4 vias
  3. Vias have a center to center separation of 2mm.

Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 6-6 illustrates an example layout.

TLK105L TLK106L example_layout_llseb8.gifFigure 6-6 Example Layout