JAJSDQ3A July   2017  – August 2017 TLV07

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV07
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Characteristics
      2. 7.3.2 Phase-Reversal Protection
      3. 7.3.3 Electrical Overstress
    4. 7.4 Device Functional Modes
      1. 7.4.1 Overload Recovery
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 TINA-TI™ (無料のダウンロード・ソフトウェア)
        2. 11.1.2.2 DIPアダプタ評価モジュール
        3. 11.1.2.3 ユニバーサル・オペアンプ評価モジュール
        4. 11.1.2.4 TI Precision Designs
        5. 11.1.2.5 WEBENCH Filter Designer
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.(1)
MIN MAX UNIT
Supply voltage –20 20 V
Single supply voltage 40 V
Signal input pin voltage (V–) – 0.5 (V+) + 0.5 V
Signal input pin current –10 10 mA
Output short-circuit current(2) Continuous
Operating ambient temperature, TA –40 125 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VS Supply voltage (VS = V+ – V–) 2.7 36 V
TA Operating temperature –40 125 °C

6.4 Thermal Information: TLV07

THERMAL METRIC TLV07 UNIT
D (SOIC)
8 PINS
RθJA Junction-to-ambient thermal resistance 149.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 97.9 °C/W
RθJB Junction-to-board thermal resistance 87.7 °C/W
ψJT Junction-to-top characterization parameter 35.5 °C/W
ψJB Junction-to-board characterization parameter 89.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W

6.5 Electrical Characteristics

at TA = 25°C, V+ = +15 V, V- = -15 V, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 50 ±100 µV
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±0.9 µV/°C
PSRR Input offset voltage vs power supply VS = 2.7 V to 36 V 0.3 µV/V
INPUT BIAS CURRENT
IB Input bias current ±40 pA
TA = –40°C to 125°C ±3 nA
IOS Input offset current ±4 pA
NOISE
Input voltage noise ƒ = 0.1 Hz to 10 Hz 2.7 µVPP
en Input voltage noise density ƒ = 1 kHz 19 nV/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range (V–) – 0.1 (V+) – 2 V
CMRR Common-mode rejection ratio VS = ±18 V, (V–) - 0.1 V < VCM < (V+) – 2 V 104 120 dB
INPUT IMPEDANCE
Differential 100 || 3 MΩ || pF
Common-mode 6 || 3 1012 Ω || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.35 V < VO < (V+) – 0.35 V 110 130 dB
FREQUENCY RESPONSE
GBP Gain bandwidth product 1 MHz
SR Slew rate G = 1 0.4 V/µs
tS Settling time To 0.1%, VS = ±18 V, G = +1, 10-V step 20 µs
To 0.01% (12-bit), VS = ±18 V
G = 1
10-V step		 28 µs
OUTPUT
VO Voltage output swing from rail RL = 10 kΩ 120 mV
ISC Short-circuit current 17 mA
RO Open-loop output resistance ƒ = 1 MHz
IO = 0 A		 900 Ω
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 A 930 1800 µA
TEMPERATURE
Specified range –40 125 °C
Operating range –40 125 °C

6.6 Typical Characteristics

VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)

Table 1. Characteristic Performance Measurements

DESCRIPTION FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Distribution Figure 2
Offset Voltage vs Temperature Figure 3
Offset Voltage vs Common-Mode Voltage Figure 4
Offset Voltage vs Power Supply Figure 5
IB and IOS vs Common-Mode Voltage Figure 6
Input Bias Current vs Temperature Figure 7
Output Voltage Swing vs Output Current (Maximum Supply) Figure 8
CMRR and PSRR vs Frequency (Referred-to-Input) Figure 9
CMRR vs Temperature Figure 10
PSRR vs Temperature Figure 11
0.1-Hz to 10-Hz Noise Figure 12
Input Voltage Noise Spectral Density vs Frequency Figure 13
THD+N Ratio vs Frequency Figure 14
THD+N vs Output Amplitude Figure 15
Quiescent Current vs Temperature Figure 16
Quiescent Current vs Supply Voltage Figure 17
Open-Loop Gain and Phase vs Frequency Figure 18
Closed-Loop Gain vs Frequency Figure 19
Open-Loop Gain vs Temperature Figure 20
Open-Loop Output Impedance vs Frequency Figure 21
No Phase Reversal Figure 22
Positive Overload Recovery Figure 23
Negative Overload Recovery Figure 24
Small-Signal Step Response Figure 25, Figure 26
Large-Signal Step Response Figure 27, Figure 28
Large-Signal Settling Time Figure 29
Short-Circuit Current vs Temperature Figure 30
Maximum Output Voltage vs Frequency Figure 31
EMIRR IN+ vs Frequency Figure 32
TLV07 C002_SBOS832.png Figure 1. Input Offset Voltage Distribution
TLV07 C010_SBOS832.png Figure 3. Input Offset Voltage vs Temperature
TLV07 C017_SBOS832.png Figure 5. Offset Voltage vs Power Supply
TLV07 C014_SBOS832.png Figure 7. Input Bias Current vs Temperature
TLV07 C203_SBOS427.png Figure 9. CMRR and PSRR vs Frequency
TLV07 C012a_SBOS832.png Figure 11. PSRR vs Temperature
TLV07 C205_SBOS427.png Figure 13. Input Voltage Noise Spectral Density vs Frequency
TLV07 C207_SBOS427.png Figure 15. THD + N vs Output Amplitude
TLV07 C004_SBOS832.png Figure 17. Quiescent Current vs Supply Voltage
TLV07 C202_SBOS427.png Figure 19. Closed-Loop Gain vs Frequency
TLV07 G022_BOS557.gif Figure 21. Open-Loop Output Impedance vs Frequency
TLV07 C211_SBOS727.png Figure 23. Positive Overload Recovery
TLV07 C214_SBOS427.png
G = +1 V/V
Figure 25. Small-Signal Step Response
TLV07 C212_SBOS427.png
G = +1 V/V
Figure 27. Large-Signal Step Response
TLV07 C216_SBOS427.png
10-V positive step
Figure 29. Large-Signal Settling Time
TLV07 C217_SBOS427.png Figure 31. Maximum Output Voltage vs Frequency
TLV07 C001_SBOS832.png Figure 2. Input Offset Voltage Drift Distribution
TLV07 C003_SBOS832.png Figure 4. Input Offset Voltage vs Common-Mode Voltage
TLV07 C013_SBOS832.png Figure 6. IB and IOS vs Common Mode Voltage
TLV07 G009_BOS557.gif Figure 8. Output Voltage Swing vs Output Current (Maximum Supply)
TLV07 C011_SBOS832.png Figure 10. CMRR vs Temperature
TLV07 C204_SBOS427.png Figure 12. 0.1-Hz to 10-Hz Noise
TLV07 C206_SBOS427.png Figure 14. THD + N Ratio vs Frequency
TLV07 C007_SBOS832.png Figure 16. Quiescent Current vs Temperature
TLV07 C201_SBOS427.png Figure 18. Open-Loop Gain and Phase vs Frequency
TLV07 C005_SBOS832.png Figure 20. Open-Loop Gain vs Temperature
TLV07 C209_SBOS427.png Figure 22. No Phase Reversal
TLV07 C210_SBOS727.png Figure 24. Negative Overload Recovery
TLV07 C215_SBOS427.png
G = –1 V/V
Figure 26. Small-Signal Step Response
TLV07 C213_SBOS427.png
G = –1 V/V
Figure 28. Large-Signal Step Response
TLV07 G034_BOS557.png
Figure 30. Short-Circuit Current vs Temperature
TLV07 G036_BOS557.gif Figure 32. EMIRR IN+ vs Frequency