The TLV2553 is a 12-bit, switched-capacitor, successive-approximation, analog-to-digital converter. The ADC has three control inputs [chip select (CS), the input-output clock, and the address/control input (DATAIN)], designed for communication with the serial port of a host processor or peripheral through a serial 3-state output.
In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages using configuration register 1. The sample-and-hold function is automatic. At the end of conversion, when programmed as EOC, the pin 19 output goes high to indicate that conversion is complete. The converter incorporated in the device features differential, high- impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range.
The TLV2553I is characterized for operation from
TA = –40°C to 85°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLV2553IPW | TSSOP (20) | 6.50 mm × 4.40 mm |
TLV2553IDW | SOIC (20) | 12.80 mm × 7.50 mm |
Changes from B Revision (September 2002) to C Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AIN0 to AIN10 | 1 to 9, 11, 12 | I | Analog input. These 11 analog-signal inputs are internally multiplexed. |
CS | 15 | I | Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT, DATA IN, and I/O CLOCK. A low-to-high transition disables DATA IN and I/O CLOCK within a setup time. |
DATA IN | 17 | I | Serial data input. The 4-bit serial data can be used as address selects the desired analog input channel or test voltage to be converted next, or a command to activate other features. The input data is presented with the MSB (D7) first and is shifted in on the first four rising edges of the I/O CLOCK. After the four address/command bits are read into the command register CMR, I/O CLOCK clocks the remaining four bits of configuration in. |
DATA OUT | 16 | O | 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when CS is high and active when CS is low. With a valid CS, DATA OUT is removed from the high-impedance state and is driven to the logic level corresponding to the MSB/LSB value of the previous conversion result. The next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB/LSB, and the remaining bits are shifted out in order. |
EOC | 19 | O | End-of-convertions status. Used to indicate the end of conversion (EOC) to the host processor. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and remains low until the conversion is complete and the data is ready for transfer. |
GND | 10 | — | Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND. |
I/O CLOCK | 18 | I |
Input /output clock. I/O CLOCK receives the serial input and performs the following four functions:
|
REF+ | 14 | I/O | Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The maximum analog input voltage range is determined by the difference between the voltage applied to terminals REF+ and REF–. |
REF– | 13 | I/O | Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF–. This pin is connected to analog ground (GND of the ADC) when internal reference is used. |
VCC | 20 | — | Positive supply voltage |