SLOS351E February   2004  – November 2016 TLV271 , TLV272 , TLV274

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information: TLV271
    4. 7.4  Thermal Information: TLV272
    5. 7.5  Thermal Information: TLV274
    6. 7.6  Electrical Characteristics: DC Characteristics
    7. 7.7  Electrical Characteristics: Input Characteristics
    8. 7.8  Electrical Characteristics: Output Characteristics
    9. 7.9  Electrical Characteristics: Power Supply
    10. 7.10 Electrical Characteristics: Dynamic Performance
    11. 7.11 Electrical Characteristics: Noise/Distortion Performance
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail to Rail Output
      2. 8.3.2 Offset Voltage
      3. 8.3.3 Driving a Capacitive Load
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
      1. 9.3.1 General Configurations
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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メカニカル・データ（パッケージ｜ピン）
  • D|8
  • P|8
  • DBV|5
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発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply, VDD 16.5 V
Differential input, VID –VDD VDD V
Input, VI −0.2 VDD + 0.2 V
Current Input, II –10 10 mA
Output, IO –100 100 mA
Temperature Operating, TA C-suffix 0 70 °C
I-suffix –40 125 °C
Junction, TJ 150 °C
Storage, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to GND.

7.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, VDD Single-supply 2.7 16 V
Split-supply ±1.35 ±8
Common-mode input voltage, VICR 0 VDD −1.35 V
Operating free-air temperature, TA C-suffix 0 70 °C
I-suffix –40 125

7.3 Thermal Information: TLV271

THERMAL METRIC(1) TLV271 UNIT
D
(SOIC)		 DBV
(SOT-23)		 P
(PDIP)
8 PINS 5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 127.2 221.7 49.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 71.6 144.7 39.4 °C/W
RθJB Junction-to-board thermal resistance 68.2 49.7 26.4 °C/W
ψJT Junction-to-top characterization parameter 22 26.1 15.4 °C/W
ψJB Junction-to-board characterization parameter 67.6 49 26.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.4 Thermal Information: TLV272

THERMAL METRIC(1) TLV272 UNIT
D
(SOIC)		 DGK
(VSSOP)		 P
(PDIP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 127.2 186.6 49.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 71.6 78.8 39.4 °C/W
RθJB Junction-to-board thermal resistance 68.2 107.9 26.4 °C/W
ψJT Junction-to-top characterization parameter 22 15.5 15.4 °C/W
ψJB Junction-to-board characterization parameter 67.6 106.3 26.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information: TLV274

THERMAL METRIC(1) TLV274 UNIT
D
(SOIC)		 N
(PDIP)		 PW
(TSSOP)
14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 97 66.3 135 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 56 20.5 45 °C/W
RθJB Junction-to-board thermal resistance 53 26.8 66 °C/W
ψJT Junction-to-top characterization parameter 19 2.1 n/a °C/W
ψJB Junction-to-board characterization parameter 46 26.2 60 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Electrical Characteristics: DC Characteristics

at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
VIO Input offset voltage VIC = VDD/2, RL = 10 kΩ, VO = VDD/2, RS = 50 Ω 25°C 0.5 5 mV
Full range 7
αVIO Offset voltage drift 25°C 2 µV/°C
CMRR Common-mode rejection ratio VIC = 0 to VDD − 1.35 V,
RS = 50 Ω		 VDD = 2.7 V 25°C 58 70 dB
Full range 55
VIC = 0 to VDD − 1.35 V,
RS = 50 Ω		 VDD = 5 V 25°C 65 80
Full range 62
VIC = –5 V to VDD − 1.35 V,
RS = 50 Ω		 VDD = ±5 V 25°C 69 85
Full range 66
AVD Large-signal differential voltage amplification VO(PP) = VDD/2,
RL = 10 kΩ		 VDD = 2.7 V 25°C 97 106 dB
Full range 76
VDD = 5 V 25°C 100 110
Full range 86
VDD = ±5 V 25°C 100 115
Full range 90
(1) Full range is 0°C to 70°C for C-suffix and full range is –40°C to 125°C for I-suffix. If not specified, full range is –40°C to 125°C.

7.7 Electrical Characteristics: Input Characteristics

at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted).
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
IIO Input offset current VDD = 5 V, VIC = VDD/2,
VO = VDD/2, RS = 50 Ω		 25°C 1 60 pA
70°C 100
125°C 1000
IIB Input bias current VDD = 5 V, VIC = VDD/2,
VO = VDD/2, RS = 50 Ω		 25°C 1 60 pA
70°C 100
125°C 1000
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 21 kHz 25°C 8 pF

7.8 Electrical Characteristics: Output Characteristics

at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted).
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
VOH High-level output voltage VIC = VDD/2, IOH = –1 mA VDD = 2.7 V 25°C 2.55 2.58 V
Full range 2.48
VDD = 5 V 25°C 4.9 4.93
Full range 4.85
VDD = ±5 V 25°C 4.92 4.96
Full range 4.9
VIC = VDD/2, IOH = –5 mA VDD = 2.7 V 25°C 1.9 2.1
Full range 1.5
VDD = 5 V 25°C 4.6 4.68
Full range 4.5
VDD = ±5 V 25°C 4.7 4.84
Full range 4.65
VOL Low-level output voltage VIC = VDD/2, IOH = 1 mA VDD = 2.7 V 25°C 0.1 0.15 V
Full range 0.22
VDD = 5 V 25°C 0.05 0.1
Full range 0.15
VDD = ±5 V 25°C –4.95 –4.92
Full range –4.9
VIC = VDD/2, IOH = 5 mA VDD = 2.7 V 25°C 0.5 0.7
Full range 1.1
VDD = 5 V 25°C 0.28 0.4
Full range 0.5
VDD = ±5 V 25°C –4.84 –4.7
Full range –4.65
IO Output current VO = 0.5 V from rail,
VDD = 2.7 V		 Positive rail 25°C 4 mA
Negative rail 25°C 5
VO = 0.5 V from rail,
VDD = 5 V		 Positive rail 25°C 7
Negative rail 25°C 8
VO = 0.5 V from rail,
VDD = 10 V		 Positive rail 25°C 13
Negative rail 25°C 12

7.9 Electrical Characteristics: Power Supply

at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless otherwise noted).
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
IDD Supply current
(per channel)		 VO = VDD/2 VDD = 2.7 V 25°C 470 560 µA
VDD = 5 V 25°C 550 660
VDD = 10 V 25°C 625 800
Full range 1000
PSRR Supply voltage rejection ratio
(ΔVDD /ΔVIO)		 VDD = 2.7 V to 16 V, VIC = VDD/2, no load 25°C 70 80 dB
Full range 65
(1) Full range is 0°C to 70°C for C-suffix and full range is –40°C to 125°C for I-suffix. If not specified, full range is –40°C to 125°C.

7.10 Electrical Characteristics: Dynamic Performance

over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
UGBW Unity-gain bandwidth RL = 2 kΩ, CL = 10 pF VDD = 2.7 V 25°C 2.4 MHz
VDD = 5 V to 10 V 25°C 3
SR Slew rate at unity gain VO(PP) = VDD/2,
CL = 50 pF,
RL = 10 kΩ		 VDD = 2.7 V 25°C 1.35 2.1 V/µs
Full range 1
VDD = 5 V 25°C 1.45 2.4 V/µs
Full range 1.2
VDD = ±5 V 25°C 1.8 2.6 V/µs
Full range 1.3
φm Phase margin RL = 2 kΩ CL = 10 pF 25°C 65 °
Gain margin RL = 2 kΩ CL = 10 pF 25°C 18 dB
tS Setting time VDD = 2.7 V,
V(STEP)PP = 1 V,
AV = –1,
CL = 10 pF
RL = 2 kΩ		 0.1% 25°C 2.9 µs
VDD = 5 V, ±5 V
V(STEP)PP = 1 V,
AV = –1,
CL = 47 pF
RL = 2 kΩ		 0.1% 2
(1) Full range is 0°C to 70°C for C suffix and full range is –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.

7.11 Electrical Characteristics: Noise/Distortion Performance

over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
THD + N Total harmonic distortion plus noise VDD = 2.7 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ , f = 10 kHz		 AV = 1 25°C 0.02%
AV = 10 0.05%
AV = 100 0.18%
VDD = 5 V, ±5 V,
VO(PP) = VDD/2 V,
RL = 2 kΩ , f = 10 kHz		 AV = 1 25°C 0.02%
AV = 10 0.09%
AV = 100 0.5%
Vn Equivalent input noise voltage f = 1 kHz 25°C 39 nV/√Hz
f = 10 kHz 35
In Equivalent input noise current f = 1 kHz 25°C 0.6 fA /√Hz

7.12 Typical Characteristics

Table 1. Table of Graphs

DESCRIPTION FIGURE NO.
CMRR Common-mode rejection ratio vs Frequency Figure 1
Input bias and offset current vs Free-air temperature Figure 2
VOL Low-level output voltage vs Low-level output current Figure 3, Figure 5, Figure 7
VOH High-level output voltage vs High-level output current Figure 4, Figure 6, Figure 8
VO(PP) Peak-to-peak output voltage vs Frequency Figure 9
IDD Supply current vs Supply voltage Figure 10
PSRR Power-supply rejection ratio vs Frequency Figure 11
AVD Differential voltage gain and phase vs Frequency Figure 12
Gain-bandwidth product vs Free-air temperature Figure 13
SR Slew rate vs Supply voltage Figure 14
vs Free-air temperature Figure 15
φm Phase margin vs Capacitive load Figure 16
Vn Equivalent input noise voltage vs Frequency Figure 17
Voltage-follower large-signal pulse response Figure 18, Figure 19
Voltage-follower small-signal pulse response Figure 20
Inverting large-signal response Figure 21, Figure 22
Inverting small-signal response Figure 23
Crosstalk vs Frequency Figure 24
TLV271 TLV272 TLV274 tc_cmrr_fqcy_los351.gif
Figure 1. Common-Mode Rejection Ratio vs
Frequency
TLV271 TLV272 TLV274 tc_vo-low_io-low_27v_los351.gif
Figure 3. Low-Level Output Voltage vs
Low-Level Output Current
TLV271 TLV272 TLV274 tc_vo-low_io-low_5v_los351.gif
Figure 5. Low-Level Output Voltage vs
Low-Level Output Current
TLV271 TLV272 TLV274 tc_vo-low_io-low_10v_los351.gif
Figure 7. Low-Level Output Voltage vs
Low-Level Output Current
TLV271 TLV272 TLV274 tc_vo-pp_fqcy_los351.gif
Figure 9. Peak-to-Peak Output Voltage vs
Frequency
TLV271 TLV272 TLV274 tc_psrr_fqcy_los351.gif
Figure 11. Power-Supply Rejection Ratio vs
Frequency
TLV271 TLV272 TLV274 tc_g-bw_product_temp_los351.gif
Figure 13. Gain Bandwidth Product vs
Free-Air Temperature
TLV271 TLV272 TLV274 tc_slew-rate_temp_los351.gif
Figure 15. Slew Rate vs
Free-Air Temperature
TLV271 TLV272 TLV274 tc_equiv-input-noise_fqcy_los351.gif
Figure 17. Equivalent Input Noise Voltage vs
Frequency
TLV271 TLV272 TLV274 tc_v-follow_lg-sig-pulse-resp-10v_los351.gif
Figure 19. Voltage-Follower Large-Signal
Pulse Response
TLV271 TLV272 TLV274 tc_invert-lg-signal_5v_los351.gif
Figure 21. Inverting Large-Signal Response
TLV271 TLV272 TLV274 tc_invert-sm-signal_5v_los351.gif
Figure 23. Inverting Small-Signal Response
TLV271 TLV272 TLV274 tc_ibias-offset_temp_los351.gif
Figure 2. Input Bias and Offset Current vs
Free-Air Temperature
TLV271 TLV272 TLV274 tc_vo-hi_io-hi_27v_los351.gif
Figure 4. High-Level Output Voltage vs
High-Level Output Current
TLV271 TLV272 TLV274 tc_vo-hi_io-hi_5v_los351.gif
Figure 6. High-Level Output Voltage vs
High-Level Output Current
TLV271 TLV272 TLV274 tc_vo-hi_io-hi_10v_los351.gif
Figure 8. High-Level Output Voltage vs
High-Level Output Current
TLV271 TLV272 TLV274 tc_vsup-isup_los351.gif
Figure 10. Supply Current vs
Supply Voltage
TLV271 TLV272 TLV274 tc_diff_volt_gain_phase_los351.gif
Figure 12. Differential Voltage Gain and Phase
TLV271 TLV272 TLV274 tc_slew-rate_vsupply_los351.gif
Figure 14. Slew Rate vs
Supply Voltage
TLV271 TLV272 TLV274 tc_phase-margin_cap-load_los351.gif
Figure 16. Phase Margin vs
Capacitive Load
TLV271 TLV272 TLV274 tc_v-follow_lg-sig-pulse-resp-5v_los351.gif
Figure 18. Voltage-Follower Large-Signal
Pulse Response
TLV271 TLV272 TLV274 tc_v-follow_sm-sig-pulse-resp-5v_los351.gif
Figure 20. Voltage-Follower Small-Signal
Pulse Response
TLV271 TLV272 TLV274 tc_invert-lg-signal_10v_los351.gif
Figure 22. Inverting Large-Signal Response
TLV271 TLV272 TLV274 tc_xtalk_fqcy_los351.gif
Figure 24. Crosstalk vs Frequency