JAJSE31A October   2017  – December 2018 TLV2313-Q1 , TLV313-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     EMIRR IN+と周波数との関係
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TLV313-Q1
    2.     Pin Functions: TLV2313-Q1
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TLV313-Q1
    5. 7.5 Thermal Information: TLV2313-Q1
    6. 7.6 Electrical Characteristics: 5.5 V
    7. 7.7 Electrical Characteristics: 1.8 V
    8. 7.8 Typical Characteristics: Table of Graphs
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Input
      3. 8.3.3 Rail-to-Rail Output
      4. 8.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5 Capacitive Load and Stability
      6. 8.3.6 EMI Susceptibility and Input Filtering
      7. 8.3.7 Input and ESD Protection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example: Single Channel
    3. 11.3 Layout Example: Dual Channel
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Electrical Characteristics: 5.5 V


at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2, (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.75 3 mV
dVOS/dT Input offset voltage vs temperature TA = –40°C to 125°C 2 µV/°C
PSRR Power-supply rejection ratio 74 90 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio (V–) – 0.2 V < VCM < (V+) – 1.3 V 85 dB
VCM = –0.2 V to 5.7 V 64 80
INPUT BIAS CURRENT
IB Input bias current ±1 pA
IOS Input offset current ±1 pA
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 6 µVPP
en Input voltage noise density f = 10 kHz 22 nV/√Hz
f = 1 kHz 26
in Input current noise density f = 1 kHz 5 fA/√Hz
INPUT CAPACITANCE
CIN Differential 1 pF
Common-mode 5
OPEN-LOOP GAIN
AOL Open-loop voltage gain 0.05 V < VO < (V+) – 0.05 V
RL = 100 kΩ		 104 dB
0.3 V < VO < (V+) – 0.3 V
RL = 2 kΩ		 100 110
Phase margin VS = 5 V, G = +1 65 °
FREQUENCY RESPONSE
GBW Gain-bandwidth product VS = 5 V, CL = 10 pF 1 MHz
SR Slew rate VS = 5 V, G = +1 0.5 V/µs
tS Settling time To 0.01%, VS = 5 V, 2-V step , G = +1 6 µs
Overload recovery time VS = 5 V, VIN × Gain > VS 3 µs
OUTPUT
VO Voltage output swing from supply rails RL = 100 kΩ(2) 5 20 mV
RL = 2 kΩ(2) 75 100
ISC Short-circuit current ±15 mA
RO Open-loop output impedance 2300 Ω
POWER SUPPLY
VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V
IQ Quiescent current per amplifier TA = –40°C to 125°C, VS = 5 V, IO = 0 mA 65 90 µA
Power-on time VS = 0 V to 5 V, to 90% IQ level 10 µs
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted. Over-temperature limits are based on characterization and statistical analysis.
(2) Specified by design and characterization; not production tested.