The TLV320AIC3104-Q1 supports the I ²C control protocol using 7-bit addressing and is capable of both standard and fast modes. For I 2C fast mode, note that the minimum timing for each of tHD-STA, tSU-STA, and tSU-STO is 0.9 μs, as seen in Figure 7-13. The TLV320AIC3104-Q1 responds to the I ²C address of 001 1000. I ²C is a two-wire, open\u0002drain interface supporting multiple devices and masters on a single bus. Devices on the I ²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Figure 7-13 I²C Interface Timing

Communication on the I²C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320AIC3104-Q1 can only act as a slave device.

An I ²C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted across the I ²C bus in groups of eight bits. To send a bit on the I ²C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start a communication. They do this by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I ²C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I ²C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device.

Every byte transmitted on the I²C bus, address or data, is acknowledged with an acknowledge bit. When a master finishes sending a byte (eight data bits) to a slave, the master stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master finishes reading a byte, the master pulls SDA low to acknowledge this operation to the slave. The master then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus and the master attempts to address the device, the master receives a not-acknowledge because no device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320AIC3104-Q1 also responds to and acknowledges a general call, which consists of the master issuing a command with a slave-address byte of 00h.

Figure 7-14 I²C Write

Figure 7-15 I²C Read

In the case of an I ²C register write, if the master does not issue a STOP condition, then the device enters auto\u0002increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register

Similarly, in the case of an I²C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues an acknowledge, the slave takes over control of the SDA bus and transmits for the next 8 clocks the data of the next incremental register.