JAJSMF1G April   2006  – July 2021 TLV320AIC3106

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements: Audio Data Serial Interface (1)
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right-Justified Mode
        2. 10.3.2.2 Left-Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
        3. 10.3.3.3 Stereo Audio DAC
          1. 10.3.3.3.1 Digital Audio Processing for Playback
          2. 10.3.3.3.2 Digital Interpolation Filter
          3. 10.3.3.3.3 Delta-Sigma Audio DAC
          4. 10.3.3.3.4 Audio DAC Digital Volume Control
          5. 10.3.3.3.5 Increasing DAC Dynamic Range
          6. 10.3.3.3.6 Analog Output Common-Mode Adjustment
          7. 10.3.3.3.7 Audio DAC Power Control
      4. 10.3.4  Audio Analog Inputs
      5. 10.3.5  Analog Fully Differential Line Output Drivers
      6. 10.3.6  Analog High Power Output Drivers
      7. 10.3.7  Input Impedance and VCM Control
      8. 10.3.8  General-Purpose I/O
      9. 10.3.9  Digital Microphone Connectivity
      10. 10.3.10 Micbias Generation
      11. 10.3.11 Short Circuit Output Protection
      12. 10.3.12 Jack/Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 Analog Input Bypass Path Functionality
        2. 10.4.1.2 ADC PGA Signal Bypass Path Functionality
        3. 10.4.1.3 Passive Analog Bypass During Powerdown
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 Digital Control Serial Interface
        1. 10.5.1.1 SPI Control Mode
          1. 10.5.1.1.1 SPI Communication Protocol
          2. 10.5.1.1.2 Limitation on Register Writing
          3. 10.5.1.1.3 Continuous Read / Write Operation
        2. 10.5.1.2 I2C Control Interface
          1. 10.5.1.2.1 I2C BUS Debug in a Glitched System
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Examples
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGZ|48
  • ZXH|80
サーマルパッド・メカニカル・データ
発注情報

11.2.2 Detailed Design Procedure

Using the Typical Application Schematic as a guide, integrate the hardware into the system.

Following the recommended component placement, schematic layout and routing given in the Section 13.2 section, integrate the device and its supporting components into the system PCB file.

  • For questions and support go to the E2E forums (e2e.ti.com). If it is necessary to deviate from the recommended layout, visit the E2E forum to request a layout review.

As the TLV320AIC3106 can be controlled with I2C or SPI protocol, the selection pin of the device should be connected properly.

Determining sample rate and Master clock frequency is required since powering up the device as all internal timing is derived from the master clock. See the Section 10.3.3.1 section in order to get more information of how to configure correctly the required clocks for the device.

As the TLV320AIC3106 is designed for low-power applications, when powered up, the device has several features powered down. A correct routing of the TLV320AIC3106 signals is achieved by a correct setting of the device registers, powering up the required stages of the device and configuring the internal switches to follow a desired route.

For more information of the device configuration and programming, see the TLV320AIC3106 technical documents section in ti.com (http://www.ti.com/product/TLV320AIC3106/technicaldocuments).