JAJSMF1G
April 2006 – July 2021
TLV320AIC3106
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
概要 (続き)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements: Audio Data Serial Interface (1)
8.7
Timing Diagrams
8.8
Typical Characteristics
9
Parameter Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Hardware Reset
10.3.2
Digital Audio Data Serial Interface
10.3.2.1
Right-Justified Mode
10.3.2.2
Left-Justified Mode
10.3.2.3
I2S Mode
10.3.2.4
DSP Mode
10.3.2.5
TDM Data Transfer
10.3.3
Audio Data Converters
10.3.3.1
Audio Clock Generation
10.3.3.2
Stereo Audio ADC
10.3.3.2.1
Stereo Audio ADC High-Pass Filter
10.3.3.2.2
Automatic Gain Control (AGC)
10.3.3.2.2.1
Target Level
10.3.3.2.2.2
Attack Time
10.3.3.2.2.3
Decay Time
10.3.3.2.2.4
Noise Gate Threshold
10.3.3.2.2.5
Maximum PGA Gain Applicable
10.3.3.3
Stereo Audio DAC
10.3.3.3.1
Digital Audio Processing for Playback
10.3.3.3.2
Digital Interpolation Filter
10.3.3.3.3
Delta-Sigma Audio DAC
10.3.3.3.4
Audio DAC Digital Volume Control
10.3.3.3.5
Increasing DAC Dynamic Range
10.3.3.3.6
Analog Output Common-Mode Adjustment
10.3.3.3.7
Audio DAC Power Control
10.3.4
Audio Analog Inputs
10.3.5
Analog Fully Differential Line Output Drivers
10.3.6
Analog High Power Output Drivers
10.3.7
Input Impedance and VCM Control
10.3.8
General-Purpose I/O
10.3.9
Digital Microphone Connectivity
10.3.10
Micbias Generation
10.3.11
Short Circuit Output Protection
10.3.12
Jack/Headset Detection
10.4
Device Functional Modes
10.4.1
Bypass Path Mode
10.4.1.1
Analog Input Bypass Path Functionality
10.4.1.2
ADC PGA Signal Bypass Path Functionality
10.4.1.3
Passive Analog Bypass During Powerdown
10.4.2
Digital Audio Processing for Record Path
10.5
Programming
10.5.1
Digital Control Serial Interface
10.5.1.1
SPI Control Mode
10.5.1.1.1
SPI Communication Protocol
10.5.1.1.2
Limitation on Register Writing
10.5.1.1.3
Continuous Read / Write Operation
10.5.1.2
I2C Control Interface
10.5.1.2.1
I2C BUS Debug in a Glitched System
10.6
Register Maps
10.6.1
Output Stage Volume Controls
11
Application and Implementation
11.1
Application Information
11.2
Typical Application
11.2.1
Design Requirements
11.2.2
Detailed Design Procedure
11.2.3
Application Curves
12
Power Supply Recommendations
13
Layout
13.1
Layout Guidelines
13.2
Layout Examples
14
Device and Documentation Support
14.1
Receiving Notification of Documentation Updates
14.2
サポート・リソース
14.3
Trademarks
14.4
Electrostatic Discharge Caution
14.5
Glossary
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
RGZ|48
ZXH|80
サーマルパッド・メカニカル・データ
RGZ|48
QFND031W
発注情報
jajsmf1g_oa
jajsmf1g_pm
11.2.3
Application Curves
Figure 11-2
Total Harmonic Distortion vs Headphone Out Power
Figure 11-3
MICBIAS Voltage vs Supply Voltage