SLAS647C December 2009 – May 2016 TLV320AIC3110
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
This typical connection highlights the required external components and system level connections for proper operation of the device in several popular use cases.
Each of these configurations can be realized using the Evaluation Modules (EVMs) for the device. These flexible modules allow full evaluation of the device in the most common modes of operation. Any design variation can be supported by TI through schematic and layout reviews. Visit http://e2e.ti.com for design assistance and join the audio amplifier discussion forum for additional information.
The following application shows the minimal requirements and connections for the TLV320AIC3110 usage. This application shows the usage of a microphone input (MIC1RP), line input (MIC1LP, MIC1LM), headphone output (HPLOUT, HPROUT) and speaker output (SPKP, SPKM). Additionally, a host processor is used for I2C control and Data Interface.
For this design example, use the parameters listed in Table 8-1 as the input parameters.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
AVDD | 3.3 V |
DVDD | 1.8 V |
HPVDD | 3.3 V |
IOVDD | 3.3 A |
Maximum MICBIAS current | 4 mA |
SPKVDD | 5 V |
Power consumption (record) | 9.24 mW (PRB_R5, 48 kHz, AOSR = 128) |
Power consumption (playback) | 25.62 mW (PRB_P1, 48 kHz, DOSR = 128, stereo headphones) |
Using Figure 8-1 as a guide, integrate the hardware into the system.
Following the recommended component placement, schematic layout and routing given in Section 10, integrate the device and its supporting components into the system PCB file.
Determining sample rate and master clock frequency is required since powering up the device as all internal timing is derived from the master clock. Refer to Section 7.3.11 to get more information of how to configure correctly the required clocks for the device.
As the TLV320AIC3110 is designed for low-power applications, when powered up, the device has several features powered down. A correct routing of the TLV320AIC3110 signals is achieved by a correct setting of the device registers, powering up the required stages of the device and configuring the internal switches to follow a desired route. For more information of the device configuration and programming, refer to the TLV320AIC3110's technical documents on ti.com.